Specifying Burst Mode - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

When specifying burst-mode for interfaces, using the max_read_burst_length or max_write_burst_length options (as described in the Syntax section). There are limitations and related considerations that are derived from the AXI standard:

The burst length should be less than, or equal to 256 words per transaction, because ARLEN & AWLEN are 8 bits; the actual burst length is AxLEN+1. In total, less than 4 KB is transferred per burst transaction. Do not cross the 4 KB address boundary. The bus width is specified as a power of 2, between 32-bits and 512-bits (i.e. 32, 64, 128, 256, 512 bits) or in bytes: 4, 8, 16, 32, 64.

Given the 4 KB limit, the maximum burst length for a single transaction for a bus width of:

  • 32-bits is 256 words for 1024 total bytes transferred per transaction.

  • 64-bits is 256 words for 2048 total bytes transferred per transaction.

  • 128-bits is 256 words for 4096 total bytes transferred per transaction.

  • 256-bits is 128 words for 4096 total bytes transferred per transaction.

  • 512-bits is 64 words for 4096 total bytes transferred per transaction.

NOTE: The actual transactions are design dependent, for example, pipelined accesses from a for-loop of 100 iterations when max_read_burst_length or max_write_burst_length is set to 128, will not fill the max burst length. However, if accesses are longer than the specified maximum burst length, some accesses will be split into smaller bursts. For example, a pipelined for-loop with 100 accesses and max_read_burst_length or max_write_burst_length set to 64, will be split into 2 transactions, one of the max burst length (or 64) and one transaction of the remaining data (burst of length 36 words).