Set v++ Linker Options - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

Instruct the v++ Kernel Linker to connect the kernel arguments to the corresponding banks. Use the sp option to map kernel ports or kernel arguments.

  • Kernel args:

      sp = <kernel_cu_name>.<kernel_arg>:<sptag>
    • <kernel_cu_name>: The compute unit (CU) based on the kernel name, followed by _ and index, starting from the value 1. For example, the computer unit name of the vadd kernel will be vadd_1

    • <kernel_arg>: The function argument of the CU. For the vadd kernel, the kernel argument can be found in the vadd.cpp file.

    • <sptag>: Represents a memory resource available on the target platform. Valid sptag names include DDR and PLRAM. In this tutorial, target DDR[0], DDR[1], and DDR[2]. You can also do ranges: <sptag>[min:max].

  1. Define the sp command options for the vadd kernel and add this to the Makefile.

    The kernel instance name will be: vadd_1. The arguments for the vadd kernel are specified in the vadd.cpp file. The kernel argument (in1, in2, and out) should be connected to DDR[0], DDR[1], and DDR[2]. Therefore, the sp options should be:

    sp = vadd_1.in1:DDR[0]
    sp = vadd_1.in2:DDR[1]
    sp = vadd_1.out:DDR[2]
    • Argument in1 accesses DDR Bank0

    • Argument in2 accesses DDR Bank1

    • Argument out accesses DDR Bank2.

    The three sp options are added in connectivity.cfg file.

  2. Config file is added into v++ linker options when we run the design with LAB=run2:

    ifneq ($(LAB),$(filter $(LAB),run1))
    VPP_LINK_OPTS := --config connectivity.cfg

    Using config files is a feature for the Vitis software platform. You can put options into different files and use --config to include them in a build.

  3. Host-code remains the same even if you change the bank connection. Below lines infer the bank connection and create buffers in appropriate bank automatically from kernel.group_id(N).

    auto bo0 = xrt::bo(device, vector_size_bytes, krnl.group_id(0));
    auto bo1 = xrt::bo(device, vector_size_bytes, krnl.group_id(1));
    auto bo_out = xrt::bo(device, vector_size_bytes, krnl.group_id(2));
  4. Complete a clean build of the design with LAB=run2.

     make clean
     make all LAB=run2

    Again, observe the messages in the Console view during the link step; a message similar to the following displays.

    ip_name: vadd
    Creating apsys_0.xml
    INFO: [CFGEN 83-0] Port Specs:
    INFO: [CFGEN 83-0]   kernel: vadd_1, k_port: in1, sptag: DDR[0]
    INFO: [CFGEN 83-0]   kernel: vadd_1, k_port: in2, sptag: DDR[1]
    INFO: [CFGEN 83-0]   kernel: vadd_1, k_port: out, sptag: DDR[2]
    INFO: [CFGEN 83-2228] Creating mapping for argument vadd_1.in1 to DDR[0] for directive vadd_1.in1:DDR[0]
    INFO: [CFGEN 83-2228] Creating mapping for argument vadd_1.in2 to DDR[1] for directive vadd_1.in2:DDR[1]
    INFO: [CFGEN 83-2228] Creating mapping for argument vadd_1.out to DDR[2] for directive vadd_1.out:DDR[2]

    This confirms that the Vitis core development kit has correctly mapped the kernel arguments to the specified DDR banks from the --sp options provided.

  5. Run HW-Emulation, and verify the correctness of the design.

    make run LAB=run2

After the simulation is complete, you can see the memory connections for the kernel data transfer reported as follows.

INFO: [Vitis-EM 22] [Wall clock time: 23:15, Emulation time: 0.054906 ms] Data transfer between kernel(s) and global memory(s)
vadd_1:m_axi_gmem0-DDR[0]          RD = 0.391 KB               WR = 0.000 KB
vadd_1:m_axi_gmem1-DDR[1]          RD = 0.391 KB               WR = 0.000 KB
vadd_1:m_axi_gmem2-DDR[2]          RD = 0.000 KB               WR = 0.391 KB

You can also open the xrt.run_summary and look at the Profile Summary to examine the Kernel to Global Memory section showing data transfers.

vitis_analyzer xrt.run_summary

NOTE: In the 2023.1 release, this command opens the Analysis view of the new Vitis Unified IDE and loads the run summary as described in Working with the Analysis View. You can navigate to the various reports using the left pane of the Analysis view or by clicking on the links provided in the summary report.

You will see the DDR banks assigned to each of the kernel arguments along with the traffic on each of the interfaces during HW-Emulation.

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