Second Lab - 2023.1 English

1. Change directory to the 03-dataflow_debug_and_optimization/reference-files/deadlock directory, and launch the Vitis HLS tool by issuing the following command:

   vitis_hls -p script.tcl
   

   The Vitis HLS GUI will launch and create the project needed to synthesize the design but the GUI will stop short of executing the commands in the script.tcl file.

   • Click the dropdown menu next to the green Run command () and select C Simulation (as shown below) and click OK in the C Simulation Dialog box to run simulation.

     

   • Click on the green Run command () to synthesize the design.

   • Click the dropdown menu next to the green Run command () and select Co-simulation link and then select the Channel (PIPO/FIFO) Profiling option before clicking OK in the window that pops up to run the C/RTL cosimulation. The GUI will automatically launch the Dataflow Viewer as a deadlock is detected in this design (as shown in the following figure).

     

   • Click on the green + command in the Dataflow Graph toolbar menu to expand all channels and sub-processes in the design. Processes that are deadlocked will be shown in red in the graph (as shown below). Channels that are full are displayed with red arrows in the graph, and channels that are empty are displayed with white arrows in the graph. The Channel table will additionally highlight the depth of full or empty channels in red.

   • Using both the Cosim Max Depth column and the Depth column, you can see that the first channel that you must resize is the data_channel1 that is between producer proc_1_1_U0 and consumer proc_1_2_U0 processes (as shown in the Producer and Consumer columns).

     

There are three ways to do this FIFO sizing, and this lab will walk through each one in turn:

• Manual FIFO sizing

• Global FIFO sizing

• Automated FIFO sizing