Running C Simulation and C Synthesis - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

First, you will run C simulation to confirm the optimized design works as expected. Edit the tsp.h file to make sure the number of cities is small (N=5) for faster simulation run times and Run C Simulation.

After reviewing the results of simulation, increase the number of cities again (N=13) in the tsp.h file for C synthesis so that you can compare results with the original design. Run C Synthesis.

The following figure shows the C synthesis report in the Vitis HLS GUI (the Performance and Resource Estimates section):
synthesis

You will notice that:

  • The latency for the tsp function is now less than a second.

  • The loop distance trip count is unchanged as expected since the input data is same.

  • The tripcount for the main loop (loop_compute) is now a fourth of factorial 12 (12!/4) thanks to the parallel execution of the compute function.

  • The new Loop 3 originates from the final std::min call that returns the smallest of the four results obtained.

Copyright © 2020–2023 Advanced Micro Devices, Inc

Terms and Conditions