Next, reuse the routed.dcp checkpoint file generated by the opt.tcl script to generate a new platform file (.xclbin). To do this, add the --reuse_impl option to the v++ command. This reruns the --link process using the already implemented Vivado design checkpoint file (.dcp). It runs in much less time than the initial hardware build required.
v++ -t hw --platform xilinx_u250_gen3x16_xdma_4_1_202210_1 --config design.cfg -l -o apply_watermark.hw.xilinx_u250_gen3x16_xdma_4_1_202210_1.xclbin apply_watermark.hw.xilinx_u250_gen3x16_xdma_4_1_202210_1.xo --reuse_impl ./_x/link/vivado/routed.dcp
From the transcript in the command shell, you can see that the steps to generate the implemented design have been skipped, and the bitstream generation starts.
INFO: [VPL 60-423] Target device: xilinx_u250_gen3x16_xdma_4_1_202210_1
[11:22:58] Run vpl: Step interactive: Started
Starting FPGA bitstream generation.