The RTL module Aes is the core module of AES encryption/decryption module. It uses native RTL ports interface. You can find the Verilog source code in the ~/aes/rtl directory. The signal descriptions are as follows.
| Name | Width (bits) | Direction | Description |
|---|---|---|---|
| CLK | 1 | in | Clock input |
| RESETn | 1 | in | Active-low reset input |
| DATA_INPUT | 128 | in | Input data block for encryption or decryption |
| KEY | 256 | in | AES key for encryption or decryption, when using 128/192 bit key, aligned to MSB (complement 0s to least significant bit (LSB) |
| DATA_OUTPUT | 128 | out | Output data block for encryption or decryption |
| NK | 2 | in | AES Key length: 2'b00=128bit, 2'b01=192bit, 2'b10=256bit |
| NR | 4 | in | Reserved, tie to 4'b0000 for common AES operation |
| START_CIPHER | 1 | in | When given one cycle active high trigger, cipher operation is executed (encryption or decryption). |
| START_KEYEXP | 1 | in | When given one cycle active high trigger, AES key expansion operation is executed. |
| OP_FINISH | 1 | out | When the encryption or decryption job is in progress, OP_FINISH will keep low. OP_FINISH will keep high in idle state. |
| EXP_FINISH | 1 | output | When the key expansion job is in progress, EXP_FINISH will keep low. EXP_FINISH will keep high in idle state. |