RTC_GEN Kernel Development - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

We will use following generated RTL files in our rtc_gen kernel:

  • rtc_gen_control_s_axi.v

    It is the AXI Lite slave interface to upper level system and XRT. It includes all the kernel argument as well as the kernel control signals (ap_start, ap_done, ap_idle, ap_ready). We will modify this module a little to realize the read-only register time_val.

  • rtc_gen_example_axi_read_master.sv

    It is a simple AXI Lite read master which could be called by our kernel directly. It uses four control signals to trigger the master to finish data reading tasks:

    • ctrl_start: single cycle pulse to start the master state machine

    • ctrl_done: single cycle pulse indicating the finish the AXI reading task

    • ctrl_addr_offset: base address for AXI reading operation. Kernel argument read_addr can be used to drive this signal

    • ctrl_xfer_size_in_bytes: number of byes to be read from AXI bus.

    The example master also use an AXI stream port for reading data transfer, which could be connected to FIFO like data pipeline easily.

  • rtc_gen_example_counter.sv

    The sub-module of the example AXI read master.

  • rtc_gen.v It is the example top level kernel wrapper instantiating all the submodule. We will modify this module to construct our rtc_gen kernel.

  • rt_gen_tb.sv It is an example testbench using Xilinx AXI Verification IP. We can modify this testbench to test our rtc_gen kernel.

In addition to these five files, we could also refer to rtc_gen_example_vadd.sv for the connection of AXI read master. For AXI stream port, it is simple and we don’t need the example for reference. For rtc_gen kernel, a Verilog file rtc_gen_core.v is created to finish the core function of the kernel. The function diagram of rtc_gen_core is shown in following diagram.


To make the core source code directory clean, we put all the necessary generated, newly composed or modified RTL files in ~/rtc_gen/src directory. Please review the directory for these source code files. Please note SPSR.v is a parameterized SRAM template which could be synthesized to FPGA BlockRAM.

./rtc_gen/src/rtc_gen_control_s_axi.v
./rtc_gen/src/rtc_gen_core.v
./rtc_gen/src/rtc_gen_example_axi_read_master.sv
./rtc_gen/src/rtc_gen_example_counter.sv
./rtc_gen/src/rtc_gen_tb.sv
./rtc_gen/src/rtc_gen.v
./rtc_gen/src/SPSR.v

Now we remove all the existing Verilog/SystemVerilog source codes (except for thos in IP group) from the rtc_gen_ex project in Vivado, then add the files in ./rtc_gen/src to the project (rtc_gen_tb.sv for Simulation-Only Sources, other files for Design Sources). Thus you can see the design hierarchy as below snapshot, and we finish the coding for kernel rtc_gen.


Now you can simulation the design and go through normal RTL design flow with standard Vivado design methodology. A text format font library file font_sim_data.txt in ./rtc_gen directory is provided, which could be read in by testbench rtc_gen_tb.sv for simulation. Please copy it to ./rtc_gen/vivado_project/rtc_gen_ex/rtc_gen_ex.sim/sim_1/behav/xsim/ for simulation runs.