Optimizing the Design in the Vivado Tool - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

You can optimize the Vivado implementation results to achieve your goal using various optimization techniques, to achieve timing closure for example, or to improve performance. After working with the Vivado tool to optimize your design, write a design checkpoint (DCP) from the routed design to reuse in the Vitis compiler link process (v++ --link).

IMPORTANT: Ensure that the Vitis tools and Vivado tools use the same release version.

For information on specific Vivado tool usage and optimization, refer to the Vivado Design Suite User Guide: Implementation (UG904) and the UltraFast Design Methodology Guide for FPGAs and SoCs (UG949).

You can run the Vivado tool in batch mode using a Tcl script or run it interactively. In this tutorial, you will run it interactively, and then source a Tcl script inside the tool to achieve your optimization. This will give you an opportunity to familiarize yourself with the Vivado IDE.

  1. From the /reference-file folder, launch the Vivado IDE.

    vivado
    
  2. When the Vivado IDE is open, enter the following command in the Tcl console.

    source ./opt.tcl
    

    The opt.tcl file includes the following Tcl commands:

    #DCP files in different stages of Vivado have been written by v++ linker automatically with option "-R2"
    open_checkpoint ./_x/link/vivado/vpl/prj/prj.runs/impl_1/pfm_top_wrapper_routed.dcp
    #Run post-route physical optimization
    phys_opt_design -directive AggressiveExplore
    write_checkpoint -force ./_x/link/vivado/routed.dcp
    

    After the opt.tcl script completes, if you are not familiar with the tool, spend some time looking around the Vivado IDE. Examine the Tcl console at the bottom of the IDE to see what commands have been run.

  3. Select File > Exit.