Module 3 - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
Release Date
2023.1 English

Code, files and instructions for Module 3 (same flow as in Module 1 to setup the GUI or run make).

In this module, both the kernel and host code are modified to use 32-bit floating point data types (float) instead of the 64-bit floating point (double) to show the performance and AMD utilization beneficial impact of downsizing data types.

The AMD device fitted on the U50 card is an AMD UltraScale+™ device that can implement floating point using hardware resources (DSP blocks and logic). Floating point operators tend to use a good amount of hardware. Here in this module, you can measure the savings when scaling down to 32-bit floating point types.

  • Run Vitis and hardware emulation only (as described in Module 1). No need to run software emulation or actual hardware compilation.

  • Run Vitis Analyzer to measure both the impact on the device resources and performance improvement.

  • Compare to utilization seen in previous module.

Did it shorten kernel execution time?

  • Run Vitis HLS to measure detailed parameters including the II (remember, the II is the initiation interval, the ability of the generated hardware to consume data every II clock cycle).

Are resources used less than for Modules 1 and 2? Is the II any different than before?