Manual FIFO Sizing - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

Performance losses due to insufficient FIFO or PIPO depth always cause at least one process to block on a full FIFO. Determining the right size for the FIFO depth is generally an unsolvable problem. Fortunately, RTL co-simulation also reports the maximum depth achieved for each channel so that even if you assign an arbitrarily large depth for the FIFO, you can always resize it to the max depth achieved. Additionally, increasing FIFO or PIPO depths never reduces performance, it simply consumes additional resources.

Adjusting FIFO Depth 1.

As discussed, you must resize data_channel1 that is between producer proc_1_1_U0 and consumer proc_1_2_U0 processes. In order to resize the blocked FIFO, follow these steps:

  • As the above figure shows, right-click on the highlighted data_channel1 row and select the Modify Depth option. This displays the Modify Depth dialog box as shown below.

    Modifying FIFO Depth

  • Set the new depth as 4 (double of 2), and click the OK button.

  • The GUI will ask you if you want to rerun the cosimulation. Click the No button as we are not done with modifying FIFO depths.

  • Repeat this for data_channel2 which was also part of the deadlock.

  • The GUI will ask you if you want to rerun the cosimulation. Click the Yes button, and then select the Channel (PIPO/FIFO) Profiling option before clicking OK to launch co-simulation.

  • The C/RTL co-simulation is run again and reports that the design is still deadlocked (as shown below).

    Adjusting FIFO Depth 2.

  • Now repeat the above steps and increase the depth of data_channel1 and data_channel2 to 10. Rerun C/RTL co-simulation and observe that the deadlock is no longer on these channels (now highlighted in green) but has now moved to the channels between process proc_1_U0 and proc_2_U0 (as shown below).

    Adjusting FIFO Depth 3.

  • Repeat the FIFO resizing steps on these channels and set the new depth to 10 and then rerun the C/RTL co-simulation. Notice that the deadlock has now moved to channels between process proc_2_1_U0 and proc_2_2_U0 (as shown below).

    Adjusting FIFO Depth 4.

  • Repeat the FIFO resizing steps on these channels and set the new depth to 10 and then rerun the C/RTL co-simulation. Notice that the deadlock is now resolved (as shown below).

    TIP: The Dataflow Graph may not be displayed automatically, because the deadlock issue has been resolved. You might have to manually open the Dataflow Graph viewer.

    Adjusting FIFO Depth 5.

    In the above figure, note that only three of the channels actually require a depth of 10. This can be seen by comparing the Cosim Max Depth and Depth columns. The other channels are fine with the default depths and dont require the increased depth value.

    IMPORTANT: While the deadlock has been resolved the new FIFO depths that helped resolve the issue have not been back-annotated to the source code. If you quit the Vitis HLS GUI at this point, you will loose these depth settings. Note that if you do choose to back-annotate these new depths to the source code, you will have to undo them later when you proceed to the next phase of the tutorial.

  • To back-annotate your solution to the source code, select all the channels that need the new depth setting (by pressing Ctrl and selecting the channel with a mouse click) and select the Back Annotate the New Depth into the Design option as shown below and click Next.