Kernel Integration (Linking) - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

After the three kernels are ready, the make tool calls Vitis v++ command to finish the linking job. The configuration file krnl_aurora_test.cfg designates the connection topology of the kernels.

The major part of the configuration file is as below (use U200 for example):


# AXI connection

# ---------------------------------------
# Aurora signal connection (GT / clock)
# ---------------------------------------
# uncomment following lines for xilinx_u200_gen3x16_xdma_1_202110_1

Note the last part of the configuration file, which is Aurora/GT related connection. In the above snippet, io_clk_qsfp_refclka_00 and io_gt_qsfp_00 are the GT reference clock interface and GT port interface, respectively. ii_level0_wire/ulp_m_aclk_freerun_ref_00 is the output pin for a 100MHz clock. These interfaces and clock pins information can be obtained by Vivado command platforminfo –verbose. Or you can also open the auto created Vivado project ULP block design to view these port/interface/signal name. Note that the default uncommented lines in the krnl_aurora_test.cfg file is for Alveo U200 card. If you using other supported Alveo cards, uncomment the relevant lines according to your card model.

Note that We have known the AXI stream ports of the Aurora IP work on 256 bits on around 161 MHz, and the external AXI stream ports of krnl_aurora is connected to 300 MHz kernel clock by default in the linking stage, so there is no performance bottleneck here. In the higher lane speed case, it might not be the case, which is explained later.

The hardware linking step is finished by this command:

make xclbin PART=xxxx PLATFORM=xxx

Here, PLATFORM is the Alveo target platform that you are using, and the PART is the matching FPGA part number. You can find the applicable PLATFORM and PART string in the Makefile. If no PART and PLATFORM variables are assigned explicitly, the default PART and PLATFORM strings in the Makefile are for Alveo U200 card. Do not forget to modify relevant lines of krnl_aurora_test.cfg file if you are not using U200 card.

After issuing make command, the full hardware building flow goes through from the beginning according to the dependency, including IP generation, RTL kernel packaging, HLS kernel compilation, and finally linking to generate hardware container (XCLBIN) file.

After the building finishes, use thefollowing command to launch Vivado to open the auto generated link project to review the implementation result, including block design, timing, floorplan, etc.

vivado ./_x/link/vivado/vpl/prj/prj.xpr &

Following is the screenshot of portion of the block design for User Level Partition (ULP) with U200 card as the example. Check that all ports of krnl_aurora are connected correctly.

ULP Block Design

Following is the timing result and placement information of the implemented hardware in U200 case.

ULP Block Design