Host Programming - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

For host programming, use the XRT Native C++ APIs to control the kernel execution in the FPGA. The XRT Native APIs are very straightforward and intuitive. They provide higher efficiency compared to XRT OpenCL™, especially in those cases needing very frequent host-kernel interactions. For more details on XRT Native APIs, refer to XRT Native APIs.

The host program generates the random data as plain input, then uses the OpenSSL AES API to generate the reference cipher data. Both AES-ECB and AES-CBC modes are tested. The PCIe data transfer is very low efficient for small blocks of data, so in the host program, you assign a number of 128-bit input data into a group, and transfer a number of groups to/from FPGA at one time. In the code, you create FPGA sub-buffers for each data group for both input and output data. From the hardware limitation, the words number in each group should be multiples of 16 and the maximum allowed value is 1008 (~16 KByte).

The host test program supports the hardware emulation (hw_emu) flow as well and will select the correct XCLBIN files for hw or hw_emu mode.

For ap_ctrl_chain execution model, the host program uses multi-threading techniques to simultaneously push multi-tasks to the kernel. In each sub-thread, a run.start() function followed by a run.wait() function is used. The program also provides a option to emulate the ap_ctrl_hs mode execution. You can see the obvious performance difference between these two modes.