Features and Design Overview - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

The following figure shows a block diagram of the design, which consists of two RTL kernels:

  • ethernet_krnl_axis_x1/4: This kernel includes one single-channel or four-channel 10G ethernet sub-system IP, one AXI control slave, and two or eight AXI stream data first in first out (FIFO) modules. The data to/from GT transciever is streamed to the AXI stream data FIFO and connected outside. The kernel use XRT ap_ctrl_hs execution model. The host program can control the ethernet IP via an AXI control slave.

  • data_fifo_krnl: This kernel just includes two AXI stream data FIFO modules, which are connected together to form the loopback datapath to externel AXI stream ports. The kernel use XRT ap_ctrl_none.

In the top level hardware topology, these two or five kernels (depends on lane number) are stitched via an AXI stream connection. The AXI control slave of kernel ethernet_krnl_axis_x1/4 is also connected to the platform. Necessary reset and clock signals including those for GT transceivers are connected to relevant resources provided by the platform.

Alveo U200
Alveo U200
GT Transciever
GT Transciever
AXI Ctrl Slave
AXI Ctrl Slave
AXI Stream
Data FIFO
AXI Stream...
AXI Stream
Data FIFO
AXI Stream...
10G Ethernet IP
10G Ethernet IP
ethernet_krnl_axis_x1
ethernet_krnl_axis_x1
AXI Stream
Data FIFO
AXI Stream...
AXI Stream
Data FIFO
AXI Stream...
data_fifo_krnl
data_fifo_krnl
Platform
Platform
QSFP Cage
QSFP Cage
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As mentioned earlier, there is no meaningful functions from this design topology, so no host program code is provided.