The Hardware Acceleration Feature Tutorials illustrate specific features or flows of Vitis, some features may not be required by all designs but are still useful for some use cases.
The landing page of Hardware Acceleration contains important information including tool version, environment settings, and a table describing the platform, kernels, and supported features or flows of each tutorial. It is strongly recommended that you review the details before starting to use the acceleration tutorials.
Tutorial |
Description |
|---|---|
This tutorial demonstrates how to use the Vitis core development kit to program an RTL kernel into an FPGA and build a Hardware Emulation using a common development flow. |
|
This tutorial demonstrates how to work with an application containing RTL and C kernels, along with various design analysis features. |
|
This tutorial demonstrates how to debug and optimize the dataflow optimization in Vitis HLS. |
|
This tutorial demonstrates how using multiple DDRs can improve data transfer between kernels and global memory. |
|
This tutorial demonstrates the flexible kernel linking process to increase the number of kernel instances on an FPGA, which improves the parallelism in a combined host-kernel system. |
|
This tutorial demonstrates how you can control the Vivado® tools flow when implementing your project. |
|
This tutorial demonstrates how you can take best advantage of HBM on platforms that support it. |
|
This tutorial demonstrates how kernels can directly access buffers host memory directly. This capability requires a compatible platform. |
|
This tutorial demonstrates how to use networking GT kernels with generated Ethernet IPs and implement them on Alveo card with Vitis flow. |
|
This tutorial demonstrates how to enable p2p transfer from one FPGA device to another using XRT API host code. |