Determine Top Level Design Specification - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

The rtc_gen kernel is required to read font library from global memory into on-chip SRAM, then output the clock image via AXI stream port. Considerting the font library reading is a one-time job, and no global memory bandwidth requirement exists during normal work, so we use 32-bit (data bus) AXI4 master interface for the font reading port to save resources. In the downstream processing pipeline, we will use XF_NPP8 format (processing 8 pixels in each clock cycle), so we select the AXI stream width as 64-bit, which could transfer eight pixels in each AXI stream transaction. For control register, we will use an AXI slave interface compatible with XRT, so we could use the standard OpenCL API to program and control the kernel.

Thus we generalize the top level design specification for rtc_gen kernel as below:

Bus interfaces

  • AXI-Lite slave interface for control

  • AXI-Lite master interface for font data loading, data width 32-bit, address width 64-bit

  • AXI stream master interface for clock digit image output, data width 64-bit

Control Register

No. Arguments Width Description
0 work_mode 1 [0]: determine the kernel working mode
0 - load font from global memory to on-chip SRAM via AXI read master
1 - output RTC digit figure via AXI steam master
1 cs_count 32 [21:0]: Centi-second counter. For example, if the system clock is 200MHz, cs_count should be set to 2,000,000
2 time_format 1 [0]: determine whether centisecond is included in the output digit images
0 - disable centiseconds output
1 - enable centiseconds output
3 time_set_val 32 Set time value for internal free-running clock:
[31:24] - hours
[23:16] - minutes
[15:8] - seconds
[7:0] - centi-seconds
4 time_set_en 1 [0]: write 1 to this bit will load the time_set_value to internal free-running clock.
5 time_val 32 Read-only regsiter for internal real-time-clock time value:
[31:24] - hours
[23:16] - minutes
[15:8] - seconds
[7:0] - centi-seconds
6 read_addr 64 AXI master pointer, this is the FPGA device buffer address for font library