Design Flow and Tutorial Steps - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

First, see the following important files of this tutorial:

├── connectivity_x1/4.cfg                 Vitis linking configuration file
├── gen_ip_x1/4.tcl                       AMD Vivado™ script to generate IP                     
├── Makefile                              Makefile for every steps
├── pack_data_fifo_kernel.tcl             Vivado script to pack data fifo kernel
├── pack_eth_x1/4_kernel.tcl              Vivado script to pack ethernet kernel
└── rtl/                                  RTL sources code for two kernels

RTL wrapper files for these two kernels are provided in the ./rtl directory. All steps are executed in command line interface, and the Makefile is used to control the flow. In the Makefile, the following lines designate Alveo U200 as the target card for the design, and you could modify this for other Alveo cards. Also, you can modify the lane number setting (default is 1).

# Target hardware setting, uncomment appropriate lines
BOARD    := u200
PLATFORM := xilinx_u200_gen3x16_xdma_2_202110_1
PART     := xcu200-fsgd2104-2-e

Now, enter the root path of the tutorial and go over the tutorial step by step.