Automated FIFO Sizing - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

Of the three approaches, the automatic FIFO sizing is the easiest but:

  • It requires repeated cosimulation runs and so may take a while to converge.

  • It is a heuristic algorithm, and in some cases, it can never converge.

The algorithm automatically increases the depth of FIFOs that block writers until performance no longer increases. It can increase some FIFO depths beyond what is reasonable and will require user inspection.

In order to use the Automated FIFO sizing flow, it will require you to restart from the beginning. Exit the Vitis HLS GUI and restart it by executing the following at the command line:

vitis_hls -p script.tcl

Next, follow these steps:

To turn on the automated FIFO sizing:

  1. Click on the green Run command (Run Icon) to rerun C Synthesis.

  2. Run C/RTL Co-simulation by selecting Co-Simulation from the dropdown menu next to the green Run command (Run Icon).

  3. Select the Dynamic Deadlock Prevention option in the Co-simulation Dialog (as shown below). Click OK to start the C/RTL co-simulation.

    Dataflow Deadlock View

  4. The C/RTL Co-simulation will run for a while attempting to find the right FIFO sizes for the channels that cause the deadlock. After some time, it will stop when the co-simulation successfully completes.

  5. Relaunch the Dataflow Viewer to see a new FIFO Sizing table along side the Process and Channel tables. This new tables documents the new FIFO sizes determined by the algorithm.

  6. You can manually back-annotate these FIFO sizes in the source code using pragmas or directives.

Dataflow Deadlock View