Add Kernel Sources - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

Document ID
XD099
Release Date
2023-08-02
Version
2023.1 English

You are ready to add RTL files into the project to package as an IP. The RTL files have been provided for you in this tutorial, but this is the point at which you would insert your own RTL code.

  1. In the Sources view, click the Add Sources command (Add Sources). The Add Sources window is displayed.

  2. Click Add or create design sources, and then click Next.

  3. Click Add Directories, browse to reference-files/src, and select the IP directory (which contains the RTL sources).

    NOTE: To add your own RTL IP, specify the required folder or files.

    Add Design Sources

  4. Select the Copy sources into project and Add sources from subdirectories.

  5. Click Finish.

    The files are added to the project, and the Vivado Design Suite automatically identifies the Vadd_A_B.v file as the top level of the design. This RTL module has an interface which is compatible with the Hardware Interface Requirements for RTL kernels as discussed in the Introduction. This can be seen in the Vadd_A_B module definition by double-clicking the file in the Sources view to open it in a Code Editor window.

    module Vadd_A_B #(
      parameter integer C_S_AXI_CONTROL_ADDR_WIDTH = 12 ,
      parameter integer C_S_AXI_CONTROL_DATA_WIDTH = 32 ,
      parameter integer C_M00_AXI_ADDR_WIDTH       = 64 ,
      parameter integer C_M00_AXI_DATA_WIDTH       = 512,
      parameter integer C_M01_AXI_ADDR_WIDTH       = 64 ,
      parameter integer C_M01_AXI_DATA_WIDTH       = 512
    )