2. RTL Kernel krnl_aurora - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

As you know that the Aurora IP AXI stream ports for the 4 lane configuration works on 256 bits at 402.8 MHz. However, the default kernel clock provided to the external AXI stream port (connected to AXI stream data FIFO) is 300 MHz during link stage. So there will be throughput mismatch issues here, which lead to data loss (the Aurora IP AXI stream port for RX does not support TREADY signal). To resolve this issue, one possible solution is to expand the external AXI stream port data width of krnl_aurora kernel. For example, you expand the external AXI stream data width to 512 bits, thus you generate the AXI stream data FIFO with 512 bits data width. So you also need a 256bit-to-512bit and another 512bit-to-256bit AXI stream data width converter IP in the krnl_aurora kernel top level module. Following is the block diagram of the krnl_aurora design with 25 Gbps lane speed.

Block Diagram 25 Gbps