2: Infer Clock, Reset, and AXI Interfaces, and Associate Them with the Clock - 2023.1 English

Vitis Tutorials: Hardware Acceleration (XD099)

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2023.1 English

First, use the ipx::infer_bus_interface command to infer ap_clk and ap_rst_n as AXI bus signals. Generally, if ap_clk is the only clock used in the RTL kernel, this command can be omitted. If you use more clocks (ap_clk_2, ap_clk_3, etc.) in the design, you must use the ipx::infer_bus_interface command to explicitly infer the ports.

ipx::infer_bus_interface ap_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::infer_bus_interface ap_rst_n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]

All AXI interfaces will be automatically inferred. In this design, these AXI ports include the following:

  • A control AXI slave port: s_axi_control

  • Four AXIS slave ports: axis_slv0 ~ 3

  • Four AXIS master ports: axis_mst0 ~ 3

  • Two AXI master ports: axi_rmst and axi_wmst.

Next, use the ipx::associate_bus_interfaces command to associate the automatically inferred AXI interfaces and reset signal to ap_clk:

ipx::associate_bus_interfaces -busif s_axi_control  -clock ap_clk [ipx::current_core]
ipx::associate_bus_interfaces -busif axi_rmst       -clock ap_clk [ipx::current_core]
ipx::associate_bus_interfaces -busif axi_wmst       -clock ap_clk [ipx::current_core]
ipx::associate_bus_interfaces -busif axis_mst0      -clock ap_clk [ipx::current_core]
ipx::associate_bus_interfaces -busif axis_slv0      -clock ap_clk [ipx::current_core]
ipx::associate_bus_interfaces -clock ap_clk -reset ap_rst_n [ipx::current_core]