Feature Tutorials - 2023.1 English

Vitis Tutorials: AI Engine (XD100)

Document ID
XD100
Release Date
2023-10-03
Version
2023.1 English

These tutorials target the VCK190 board. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials. The various columns correspond to specific features/flows supported in these tutorials and will help you identify tutorials that showcase specific flows and features that you are interested in.

Feature Tutorials

Tutorial

Platform

OS

IDE Flow

Libraries Used

HLS Kernel

x86 simulator

aie simulator

SW Emu

HW Emu

HW

Event Trace in HW

Profile in HW

AI Engine A-to-Z Flow for Linux

Base / Custom

Linux

MM2S / S2MM

Yes

Yes

Yes

Yes

Yes

A to Z Bare-metal Flow

Custom

Baremetal

Vivado, Vitis IDE

MM2S / S2MM

Yes

Yes

Yes

Using GMIO with AIE

Base

Linux

Yes

Yes

Yes

Yes

Runtime Parameter Reconfiguration

Base

Linux

MM2S / S2MM

Yes

Yes

Yes

Packet Switching

Base

Linux

MM2S / S2MM

Yes

Yes

Yes

AIE Versal Integration

Base

Linux

MM2S / S2MM

Yes

Yes

Yes

Yes

Yes

Versal System Design Clocking

Base

Linux

MM2S / S2MM

Yes

Yes

Yes

Using Floating-Point in the AIE

Base

Linux

Yes

DSP Library Tutorial

Base

Linux

DSPLib

MM2S / S2MM Variant

Yes

Debug Walkthrough Tutorial

Base

Linux

Vitis IDE

Yes

Yes

Yes

Yes

Yes

Yes

Yes

AIE DSPLib and Model Composer

Base

Linux

Simulink

DSPLib

MM2S / S2MM

Yes

Yes

Versal Emulation Waveform Analysis

Base

Linux

Traffic Generators

Yes

AXIS External Traffic Generator

Base

Linux

DSPLib

MM2S / S2MM

Yes

Yes

AIE Performance and Deadlock Analysis

Base

Linux

Yes

Yes

Yes

Yes

Implementing an IIR Filter on the AIE

Base

Linux

Vitis IDE

Yes

Yes

Post-Link Recompile of an AIE Application

Base

Linux

MM2S / S2MM

Yes

Yes

Yes

Python and C++ External Traffic Generators for AI Engine Simulation and Emulation Flows

Base

Linux

MM2S / S2MM / PolarClip

Yes

Yes

Yes

Yes

Using RTL IP with AI Engines

Custom

Linux

MM2S / S2MM

Yes

Yes

Using Verilog Traffic Generators in AIE Simulation

Base

Linux

Vivado

Yes

Yes