I/O and Clock Buffers - 2022.2 English

Vivado Design Suite User Guide : Hierarchical Design (UG905)

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2022.2 English

I/O and clock buffers are supported inside OOC modules. However, some special considerations should be taken into account depending on their use.

I/O Buffers
If an OOC port connects directly to an I/O buffer in the top level, it is recommended to move this buffer inside the OOC module for better results. This is not possible in all situations (for example, if an OOC port connects directly to an IBUF in the top level, but that IBUF also drives other logic not in the OOC module), and in those cases the logic inside the OOC module should be controlled with an HD.PARTPIN_LOCS constraint. See the Out-Of-Context Commands and Constraints for more information.
Regional Clock Buffers
If a BUFR or BUFHCE exists within the OOC module it should be locked down to a specific location. The tools then appropriately place logic driven by the buffer. However, if the BUFR or BUFHCE is in the top-level design, and the OOC Pblock spans more clock regions than the buffer has access to, then more information must be supplied. A nested Pblock must be created with a range that is a subset of the range defined by the OOC Pblock. The nested Pblock would contain all of the cells driven by the BUFR or BUFHCE, and can be created with the following commands:
create_pblock -parent <parent_pblock_name> <nested_pblock_name>
add_cells_to_pblock <nested_pblock_name> -cells [get_cells -of [get_nets -segments -of [get_ports [list <clock_port> <clock_port>]]] -filter "(IS_PRIMITIVE)"]
resize_pblock <nested_pblock_name> -add {SLICE_Xx1Yy1:SLICE_Xx2Yy2}

This should be done for each module port that is driven by a BUFR or BUFHCE in the top-level. If multiple OOC clock ports have loads in the same clock regions, all applicable ports can be listed in the add_cells_to_pblock command above. The range for the nested Pblock must correspond to the BUFR or BUFHCE location in the top-level implementation. A mismatch between buffer location at the top level and the corresponding Pblock range for the OOC module can lead to an unroutable condition during top-level implementation.

Global Clock Buffers
Global buffers are supported inside an OOC module. When a BUFG is inside an OOC instance the clock net is routed on global routing in the OOC implementation. If an OOC port is driven by a clock net in the top level, the clock net is not routed during the OOC implementation, and timing estimations are used to determine clock delays/skew. The HD.CLK_SRC constraint should be used to help improve timing estimations in this case. This constraint allows the tools to know the driver location and type (for example, BUFG vs. BUFR), and to improve timing estimation by calculating clock pessimism removal (CPR). For a description of CPR, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).