Primitive: 256-Deep by 1-Wide ROM
Introduction
This design element is a 256-word by 1-bit read-only memory. The data output (O) reflects the word selected by the 8-bit address (A7:A0). The ROM is initialized to a known value during configuration with the INIT parameter. The value consists of 64 hexadecimal digits that are written into the ROM from the most-significant digit A=FH to the least-significant digit A=0H.
An error occurs if the INIT is not specified.
Logic Table
Input | Output | |||
---|---|---|---|---|
I0 | I1 | I2 | I3 | O |
0 | 0 | 0 | 0 | INIT(0) |
0 | 0 | 0 | 1 | INIT(1) |
0 | 0 | 1 | 0 | INIT(2) |
0 | 0 | 1 | 1 | INIT(3) |
0 | 1 | 0 | 0 | INIT(4) |
0 | 1 | 0 | 1 | INIT(5) |
0 | 1 | 1 | 0 | INIT(6) |
0 | 1 | 1 | 1 | INIT(7) |
1 | 0 | 0 | 0 | INIT(8) |
1 | 0 | 0 | 1 | INIT(9) |
1 | 0 | 1 | 0 | INIT(10) |
1 | 0 | 1 | 1 | INIT(11) |
1 | 1 | 0 | 0 | INIT(12) |
1 | 1 | 0 | 1 | INIT(13) |
1 | 1 | 1 | 0 | INIT(14) |
1 | 1 | 1 | 1 | INIT(15) |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | HEX | Any 256-Bit Value | All zeros | Specifies the contents of the ROM. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM
-- 7 Series
-- Xilinx HDL Language Template, version 2022.2
ROM256X1_inst : ROM256X1
generic map (
INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5, -- ROM address[5]
A6 => A6, -- ROM address[6]
A7 => A7 -- ROM address[7]
);
-- End of ROM256X1_inst instantiation
Verilog Instantiation Template
// ROM256X1: 256 x 1 Asynchronous Distributed (LUT) ROM (Mapped to four SliceM LUT6s)
// 7 Series
// Xilinx HDL Language Template, version 2022.2
ROM256X1 #(
.INIT(256'h0000000000000000000000000000000000000000000000000000000000000000) // Contents of ROM
) ROM256X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5), // ROM address[5]
.A6(A6), // ROM address[6]
.A7(A7) // ROM address[7]
);
// End of ROM256X1_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).