PLLE2_ADV - 2022.2 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2022-10-19
Version
2022.2 English

Primitive: Advanced Phase Locked Loop (PLL)

Introduction

PLLE2 is a mixed signal block designed to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide (1 to 128), phase shift, and duty cycle based on the same VCO frequency. Output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration.

PLLE2 complements the MMCM element by supporting higher speed clocking while MMCM has more features to handle most general clocking needs. PLLE2_BASE is intended for most uses of this PLL component while PLLE2_ADV is intended for use when clock switch-over or dynamic reconfiguration is required.

Port Descriptions

Port Direction Width Function
CLKFBIN Input 1 Feedback clock pin to the PLL.
CLKFBOUT Output 1 Dedicated PLL Feedback clock output.
CLKINSEL Input 1 Signal controls the state of the input MUX.
  • High = CLKIN1
  • Low = CLKIN2
CLKIN1 Input 1 Primary clock input.
CLKIN2 Input 1 Secondary clock input.
CLKOUT0 Output 1 CLKOUT0 output.
CLKOUT1 Output 1 Configurable clock output CLKOUT1.
CLKOUT2 Output 1 Configurable clock output CLKOUT2.
CLKOUT3 Output 1 Configurable clock output CLKOUT3.
CLKOUT4 Output 1 Configurable clock output CLKOUT4.
CLKOUT5 Output 1 Configurable clock output CLKOUT5.
DADDR<6:0> Input 7 The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DCLK Input 1 The DCLK signal is the reference clock for the dynamic reconfiguration port.
DEN Input 1 The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DI<15:0> Input 16 The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero.
DO<15:0> Output 16 The dynamic reconfiguration output bus provides PLL data output when using dynamic reconfiguration.
DRDY Output 1 The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the PLLs dynamic reconfiguration feature.
DWE Input 1 The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
LOCKED Output 1 An output from the PLL that indicates when the PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The PLL automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (that is., input clock phase shift). The PLL automatically reacquires lock after LOCKED is deasserted.
PWRDWN Input 1 Powers down instantiated but unused PLLs.
RST Input 1 The RST signal is an asynchronous reset for the PLL. The PLL will synchronously re-enable itself when this signal is released and go through a new phase alignment and lock cycle. A reset is required when the input clock conditions change (that is., frequency).

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
BANDWIDTH STRING "OPTIMIZED", "HIGH", "LOW" "OPTIMIZED" Specifies the PLLE2 programming algorithm affecting the jitter, phase margin and other characteristics of the PLLE2.
CLKFBOUT_MULT DECIMAL 2 to 64 5 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency.
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL.
CLKIN1_PERIOD, CLKIN2_PERIOD FLOAT (nS) 0.000 to 52.631 0.000 Specifies the input period in ns to the PLLE2 CLKIN inputs. Resolution is down to the ps. For example a value of 33.333 would indicate a 30 MHz input clock. This information is mandatory and must be supplied. CLKIN1_PERIOD relates to the input period on the CLKIN1 input while CLKIN2_PERIOD relates to the input clock period on the CLKIN2 input.
CLKOUT0_DIVIDE, CLKOUT1_DIVIDE, CLKOUT2_DIVIDE, CLKOUT3_DIVIDE, CLKOUT4_DIVIDE, CLKOUT5_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT0_DUTY _CYCLE, CLKOUT1_DUTY _CYCLE, CLKOUT2_DUTY _CYCLE, CLKOUT3_DUTY _CYCLE, CLKOUT4_DUTY _CYCLE, CLKOUT5_DUTY _CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of the associated CLKOUT clock output in percentage (for example., 0.500 will generate a 50% duty cycle).
CLKOUT0_PHASE, CLKOUT1_PHASE, CLKOUT2_PHASE, CLKOUT3_PHASE, CLKOUT4_PHASE, CLKOUT5_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL.
COMPENSATION STRING "ZHOLD", "BUF_IN", "EXTERNAL", "INTERNAL" "ZHOLD" Clock input compensation. Suggested to be set to "ZHOLD". Defines how the PLL feedback is configured.
  • "ZHOLD": PLL is configured to provide a negative hold time at the I/O registers.
  • "INTERNAL": PLL is using its own internal feedback path so no delay is being compensated.
  • "EXTERNAL": A network external to the FPGA is being compensated.
  • "BUF_IN": The configuration does not match with the other compensation modes and no delay will be compensated.
DIVCLK_DIVIDE DECIMAL 1 to 56 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
REF_JITTER1, REF_JITTER2 3 significant digit FLOAT 0.000 to 0.999 0.010 Allows specification of the expected jitter on the CLKIN inputs to better optimize PLL performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the UI percentage (the maximum peak to peak value) of the expected jitter on the input clock. REF_JITTER1 relates to the input jitter on CLKIN1 while REF_JITTER2 relates to the input jitter on CLKIN2.
STARTUP_WAIT STRING "FALSE", "TRUE" "FALSE" When "TRUE", wait for the PLLE2(s) that have this attribute attached to them will delay DONE from going high until a LOCK is achieved.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- PLLE2_ADV: Advanced Phase Locked Loop (PLL)
--            7 Series
-- Xilinx HDL Language Template, version 2022.2

PLLE2_ADV_inst : PLLE2_ADV
generic map (
   BANDWIDTH => "OPTIMIZED",  -- OPTIMIZED, HIGH, LOW
   CLKFBOUT_MULT => 5,        -- Multiply value for all CLKOUT, (2-64)
   CLKFBOUT_PHASE => 0.0,     -- Phase offset in degrees of CLKFB, (-360.000-360.000).
   -- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
   CLKIN1_PERIOD => 0.0,
   CLKIN2_PERIOD => 0.0,
   -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
   CLKOUT0_DIVIDE => 1,
   CLKOUT1_DIVIDE => 1,
   CLKOUT2_DIVIDE => 1,
   CLKOUT3_DIVIDE => 1,
   CLKOUT4_DIVIDE => 1,
   CLKOUT5_DIVIDE => 1,
   -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
   CLKOUT0_DUTY_CYCLE => 0.5,
   CLKOUT1_DUTY_CYCLE => 0.5,
   CLKOUT2_DUTY_CYCLE => 0.5,
   CLKOUT3_DUTY_CYCLE => 0.5,
   CLKOUT4_DUTY_CYCLE => 0.5,
   CLKOUT5_DUTY_CYCLE => 0.5,
   -- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
   CLKOUT0_PHASE => 0.0,
   CLKOUT1_PHASE => 0.0,
   CLKOUT2_PHASE => 0.0,
   CLKOUT3_PHASE => 0.0,
   CLKOUT4_PHASE => 0.0,
   CLKOUT5_PHASE => 0.0,
   COMPENSATION => "ZHOLD",   -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
   DIVCLK_DIVIDE => 1,        -- Master division value (1-56)
   -- REF_JITTER: Reference input jitter in UI (0.000-0.999).
   REF_JITTER1 => 0.0,
   REF_JITTER2 => 0.0,
   STARTUP_WAIT => "FALSE"    -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
   -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
   CLKOUT0 => CLKOUT0,   -- 1-bit output: CLKOUT0
   CLKOUT1 => CLKOUT1,   -- 1-bit output: CLKOUT1
   CLKOUT2 => CLKOUT2,   -- 1-bit output: CLKOUT2
   CLKOUT3 => CLKOUT3,   -- 1-bit output: CLKOUT3
   CLKOUT4 => CLKOUT4,   -- 1-bit output: CLKOUT4
   CLKOUT5 => CLKOUT5,   -- 1-bit output: CLKOUT5
   -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
   DO => DO,             -- 16-bit output: DRP data
   DRDY => DRDY,         -- 1-bit output: DRP ready
   -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
   CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock
   LOCKED => LOCKED,     -- 1-bit output: LOCK
   -- Clock Inputs: 1-bit (each) input: Clock inputs
   CLKIN1 => CLKIN1,     -- 1-bit input: Primary clock
   CLKIN2 => CLKIN2,     -- 1-bit input: Secondary clock
   -- Control Ports: 1-bit (each) input: PLL control ports
   CLKINSEL => CLKINSEL, -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
   PWRDWN => PWRDWN,     -- 1-bit input: Power-down
   RST => RST,           -- 1-bit input: Reset
   -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
   DADDR => DADDR,       -- 7-bit input: DRP address
   DCLK => DCLK,         -- 1-bit input: DRP clock
   DEN => DEN,           -- 1-bit input: DRP enable
   DI => DI,             -- 16-bit input: DRP data
   DWE => DWE,           -- 1-bit input: DRP write enable
   -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
   CLKFBIN => CLKFBIN    -- 1-bit input: Feedback clock
);

-- End of PLLE2_ADV_inst instantiation

Verilog Instantiation Template


// PLLE2_ADV: Advanced Phase Locked Loop (PLL)
//            7 Series
// Xilinx HDL Language Template, version 2022.2

PLLE2_ADV #(
   .BANDWIDTH("OPTIMIZED"),  // OPTIMIZED, HIGH, LOW
   .CLKFBOUT_MULT(5),        // Multiply value for all CLKOUT, (2-64)
   .CLKFBOUT_PHASE(0.0),     // Phase offset in degrees of CLKFB, (-360.000-360.000).
   // CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
   .CLKIN1_PERIOD(0.0),
   .CLKIN2_PERIOD(0.0),
   // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
   .CLKOUT0_DIVIDE(1),
   .CLKOUT1_DIVIDE(1),
   .CLKOUT2_DIVIDE(1),
   .CLKOUT3_DIVIDE(1),
   .CLKOUT4_DIVIDE(1),
   .CLKOUT5_DIVIDE(1),
   // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
   .CLKOUT0_DUTY_CYCLE(0.5),
   .CLKOUT1_DUTY_CYCLE(0.5),
   .CLKOUT2_DUTY_CYCLE(0.5),
   .CLKOUT3_DUTY_CYCLE(0.5),
   .CLKOUT4_DUTY_CYCLE(0.5),
   .CLKOUT5_DUTY_CYCLE(0.5),
   // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
   .CLKOUT0_PHASE(0.0),
   .CLKOUT1_PHASE(0.0),
   .CLKOUT2_PHASE(0.0),
   .CLKOUT3_PHASE(0.0),
   .CLKOUT4_PHASE(0.0),
   .CLKOUT5_PHASE(0.0),
   .COMPENSATION("ZHOLD"),   // ZHOLD, BUF_IN, EXTERNAL, INTERNAL
   .DIVCLK_DIVIDE(1),        // Master division value (1-56)
   // REF_JITTER: Reference input jitter in UI (0.000-0.999).
   .REF_JITTER1(0.0),
   .REF_JITTER2(0.0),
   .STARTUP_WAIT("FALSE")    // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_ADV_inst (
   // Clock Outputs: 1-bit (each) output: User configurable clock outputs
   .CLKOUT0(CLKOUT0),   // 1-bit output: CLKOUT0
   .CLKOUT1(CLKOUT1),   // 1-bit output: CLKOUT1
   .CLKOUT2(CLKOUT2),   // 1-bit output: CLKOUT2
   .CLKOUT3(CLKOUT3),   // 1-bit output: CLKOUT3
   .CLKOUT4(CLKOUT4),   // 1-bit output: CLKOUT4
   .CLKOUT5(CLKOUT5),   // 1-bit output: CLKOUT5
   // DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports
   .DO(DO),             // 16-bit output: DRP data
   .DRDY(DRDY),         // 1-bit output: DRP ready
   // Feedback Clocks: 1-bit (each) output: Clock feedback ports
   .CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock
   .LOCKED(LOCKED),     // 1-bit output: LOCK
   // Clock Inputs: 1-bit (each) input: Clock inputs
   .CLKIN1(CLKIN1),     // 1-bit input: Primary clock
   .CLKIN2(CLKIN2),     // 1-bit input: Secondary clock
   // Control Ports: 1-bit (each) input: PLL control ports
   .CLKINSEL(CLKINSEL), // 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2
   .PWRDWN(PWRDWN),     // 1-bit input: Power-down
   .RST(RST),           // 1-bit input: Reset
   // DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports
   .DADDR(DADDR),       // 7-bit input: DRP address
   .DCLK(DCLK),         // 1-bit input: DRP clock
   .DEN(DEN),           // 1-bit input: DRP enable
   .DI(DI),             // 16-bit input: DRP data
   .DWE(DWE),           // 1-bit input: DRP write enable
   // Feedback Clocks: 1-bit (each) input: Clock feedback ports
   .CLKFBIN(CLKFBIN)    // 1-bit input: Feedback clock
);

// End of PLLE2_ADV_inst instantiation

Related Information

  • See the 7 Series FPGAs Clocking Resource User Guide (UG472).