Primitive: Bi-Directional Differential Buffer with Input Termination Disable, Input Disable, and Differential Output
Introduction
This design element is a bidirectional differential I/O Buffer used to connect internal logic to an external bidirectional pin. This element includes an uncalibrated input termination (INTERM) disable as well as input path disable as additional power saving features when the I/O is either is an unused state or being used as an output for several clock cycles. The IOBUFDS_DIFF_OUT_INTERMDISABLE differs from the IOBUFDS_INTERMDISABLE in that it allows internal access to both phases of the differential signal. This element may only be placed in High Range (HR) banks in the 7 series devices.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
IO | In/out | 1 | Bi-directional p-side port connection. Connect directly to top-level port in the design. |
IOB | In/out | 1 | Bi-directional n-side port connection. Connect directly to top-level port in the design. |
I | Input | 1 | Buffer input representing the output path to the device. |
IBUFDISABLE | Input | 1 | Disables input path through the buffer and forces to a logic high when USE_IBUFDISABLE is set to "TRUE". If USE_IBUFDISABLE is set to "FALSE" this input is ignored and should be tied to ground. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions. |
INTERMDISABLE | Input | 1 | Disables input termination. This feature is generally used to reduce power at times when the I/O is either idle or during sustained write (output) conditions. |
TM | Input | 1 | P-side or master side of the high impedance 3-state mode when the I/O is being used for a read (input) operation. The TM pin also affects the IBUFDISABLE function when USE_IBUFDISABLE = "TRUE", and disables INTERM when in a write (output) mode. |
TS | Input | 1 | N-side or slave side of the high impedance 3-state mode when the I/O is being used for a read (input) operation. The TS pin also affects the IBUFDISABLE function when USE_IBUFDISABLE = "TRUE", and disables INTERM when in a write (output) mode. |
O | Output | 1 | Buffer p-side output representing the input path to the device. |
OB | Output | 1 | Buffer n-side output representing the input path to the device. |
Design Entry Method
Instantiation | Yes |
Inference | No |
IP Catalog | Yes |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
DIFF_TERM | STRING | "TRUE", "FALSE" | "FALSE" | Turns the built-in differential termination on (TRUE) or off (FALSE). |
IBUF_LOW_PWR | STRING | "TRUE", "FALSE" | "TRUE" | Allows a trade off of lower power consumption vs. highest performance when referenced I/O standards are used. |
IOSTANDARD | STRING | See Data Sheet | "DEFAULT" | Assigns an I/O standard to the element. |
USE_IBUFDISABLE | STRING | "TRUE", "FALSE" | "TRUE" | Enables or disables the feature of IBUFDISABLE. Generally used when it is not desirable to have the T pin disable input path to allow a read during write operation. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IOBUFDS_DIFF_OUT_INTERMDISABLE: Differential Global Clock Buffer with Differential Output
-- Input Termination and Input Path Disable
-- May only be placed in High Range (HR) Banks
-- 7 Series
-- Xilinx HDL Language Template, version 2022.2
IOBUFDS_DIFF_OUT_INTERMDISABLE_inst : IOBUFDS_DIFF_OUT_INTERMDISABLE
generic map (
DIFF_TERM => "FALSE", -- Differential Termination (TRUE/FALSE)
IBUF_LOW_PWR => "TRUE", -- Low Power - TRUE, High Performance = FALSE
IOSTANDARD => "BLVDS_25", -- Specify the I/O standard
USE_IBUFDISABLE => "TRUE") -- Use IBUFDISABLE function, "TRUE" or "FALSE"
port map (
O => O, -- Buffer p-side output
OB => OB, -- Buffer n-side output
IO => IO, -- Diff_p inout (connect directly to top-level port)
IOB => IOB, -- Diff_n inout (connect directly to top-level port)
I => I, -- Buffer input
IBUFDISABLE => IBUFDISABLE, -- input disable input, high=disable
INTERMDISABLE => INTERMDISABLE, -- Input termination disable input
TM => TM, -- 3-state enable input, high=input, low=output
TS => TS -- 3-state enable input, high=output, low=input
);
-- End of IOBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
Verilog Instantiation Template
// IOBUFDS_DIFF_OUT_INTERMDISABLE: Differential Global Clock Buffer with Differential Output
// Input Termination and Input Path Disable
// May only be placed in High Range (HR) Banks
// 7 Series
// Xilinx HDL Language Template, version 2022.2
IOBUFDS_DIFF_OUT_INTERMDISABLE #(
.DIFF_TERM("FALSE"), // Differential Termination, "TRUE"/"FALSE"
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("DEFAULT"), // Specify the input I/O standard
.USE_IBUFDISABLE("TRUE") // Set to "TRUE" to enable IBUFDISABLE feature
) IOBUFDS_DIFF_OUT_INTERMDISABLE_inst (
.O(O), // Buffer p-side output
.OB(OB), // Buffer n-side output
.IO(IO), // Diff_p inout (connect directly to top-level port)
.IOB(IOB), // Diff_n inout (connect directly to top-level port)
.I(I), // Buffer input
.INTERMDISABLE(INTERMDISABLE), // Input termination disable input
.IBUFDISABLE(IBUFDISABLE), // Input disable input, high=disable
.TM(TM), // 3-state enable input, high=input, low=output
.TS(TS) // 3-state enable input, high=input, low=output
);
// End of IOBUFDS_DIFF_OUT_INTERMDISABLE_inst instantiation
Related Information
- See the 7 Series FPGA SelectIO Resources User Guide (UG471).