IBUFDS - 2022.2 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2022-10-19
Version
2022.2 English

Primitive: Differential Signaling Input Buffer

Introduction

This design element is an input buffer that supports low-voltage, differential signaling. In IBUFDS, a design level interface signal is represented as two distinct ports (I and IB), one deemed the "master" and the other the "slave." The master and the slave are opposite phases of the same logical signal (for example, MYNET_P and MYNET_N). Optionally, a programmable differential termination feature is available to help improve signal integrity and reduce external components.

Logic Table

Inputs Outputs
I IB O
0 0 No Change
0 1 0
1 0 1
1 1 No Change

Port Descriptions

Port Direction Width Function
I Input 1 Diff_p Buffer Input.
IB Input 1 Diff_n Buffer Input.
O Output 1 Buffer Output.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

Put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the I port directly to the top-level "master" input port of the design, the IB port to the top-level "slave" input port, and the O port to the logic in which this input is to source. Specify the desired generic/defparam values to configure the proper behavior of the buffer.

Available Attributes

Attribute Type Allowed Values Default Description
DIFF_TERM BOOLEAN TRUE, FALSE FALSE Turns the built-in differential termination on (TRUE) or off (FALSE).
IBUF_LOW_PWR BOOLEAN TRUE, FALSE TRUE When set to TRUE, allows for reduced power when using differential or referenced (requiring VREF) input standards like LVDS or HSTL. A setting of FALSE demands more power but delivers higher performance characteristics. Consult the 7 Series FPGA SelectIO Resources User Guide (UG471) for details.
IOSTANDARD STRING See Data Sheet. "DEFAULT" Assigns an I/O standard to the element.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IBUFDS: Differential Input Buffer
--         7 Series
-- Xilinx HDL Language Template, version 2022.2

IBUFDS_inst : IBUFDS
generic map (
   DIFF_TERM => FALSE, -- Differential Termination
   IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD => "DEFAULT")
port map (
   O => O,  -- Buffer output
   I => I,  -- Diff_p buffer input (connect directly to top-level port)
   IB => IB -- Diff_n buffer input (connect directly to top-level port)
);

-- End of IBUFDS_inst instantiation

Verilog Instantiation Template


// IBUFDS: Differential Input Buffer
//         7 Series
// Xilinx HDL Language Template, version 2022.2

IBUFDS #(
   .DIFF_TERM("FALSE"),       // Differential Termination
   .IBUF_LOW_PWR("TRUE"),     // Low power="TRUE", Highest performance="FALSE"
   .IOSTANDARD("DEFAULT")     // Specify the input I/O standard
) IBUFDS_inst (
   .O(O),  // Buffer output
   .I(I),  // Diff_p buffer input (connect directly to top-level port)
   .IB(IB) // Diff_n buffer input (connect directly to top-level port)
);

// End of IBUFDS_inst instantiation

Related Information

  • See the 7 Series FPGA SelectIO Resources User Guide (UG471).