Macro: Synchronous First-In, First-Out (FIFO) RAM Buffer
Introduction
FPGA devices contain several block RAM memories that can be configured as general-purpose 36 Kb or 18 Kb RAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFO can be configured as an 18 Kb or 36 Kb memory. This unimacro configures the FIFO such that it uses one clock for reading as well as writing.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
ALMOSTEMPTY | Output | 1 | Almost all valid entries in FIFO have been read. |
ALMOSTFULL | Output | 1 | Almost all entries in FIFO memory have been filled. |
DO | Output | See Port Configuration table. | Data output bus addressed by ADDR. |
EMPTY | Output | 1 | FIFO is empty. |
FULL | Output | 1 | All entries in FIFO memory are filled. |
RDCOUNT | Output | See Port Configuration table. | FIFO data read pointer. |
RDERR | Output | 1 | When the FIFO is empty, any additional read operation generates an error flag. |
WRCOUNT | Output | See Port Configuration table. | FIFO data write pointer. |
WRERR | Output | 1 | When the FIFO is full, any additional write operation generates an error flag. |
CLK | Input | 1 | Clock for Read/Write domain operation. |
DI | Input | See Port Configuration table. | Data input bus addressed by ADDR. |
RDEN | Input | 1 | Read Enable |
RST | Input | 1 | Asynchronous reset. |
WREN | Input | 1 | Write Enable |
Port Configuration
This unimacro
is a parameterizable version of the primitive, and can be instantiated
only. Use this table to correctly configure the unimacro to meet design
needs.
DATA_WIDTH | FIFO_SIZE | WRCOUNT | RDCOUNT |
---|---|---|---|
72 - 37 | 36 Kb | 9 | 9 |
36 - 19 | 36 Kb | 10 | 10 |
18 Kb | 9 | 9 | |
18 - 10 | 36 Kb | 11 | 11 |
18 Kb | 10 | 10 | |
9-5 | 36 Kb | 12 | 12 |
18 Kb | 11 | 11 | |
1-4 | 36 Kb | 13 | 13 |
18 Kb | 12 | 12 |
Design Entry Method
This unimacro is a parameterizable version of the primitive, and can be
instantiated only. Consult the Port Configuration section to correctly configure
this element to meet your design needs.
Instantiation | Yes |
Inference | No |
IP Catalog | No |
Macro support | Recommended |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
ALMOST_EMPTY _OFFSET | HEX | 13-bit HEX | All zeros | Setting determines the difference between EMPTY and ALMOSTEMPTY conditions. Must be set using hexadecimal notation. |
ALMOST_FULL _OFFSET | HEX | 13-bit HEX | All zeros | Setting determines the difference between FULL and ALMOSTFULL conditions. Must be set using hexadecimal notation. |
DATA_WIDTH | INTEGER | 1 - 72 | 4 | Width of DI/DO bus. |
DEVICE | STRING | "7SERIES" | "7SERIES" | Target hardware architecture. |
DO_REG | BINARY | 0,1 | 1 |
DO_REG must be set to 0 for flags and data to follow a standard synchronous FIFO operation. When DO_REG is set to 1, effectively a pipeline register is added to the output of the synchronous FIFO. Data then has a one clock cycle latency. However, the clock-to-out timing is improved. |
FIFO_SIZE | STRING | "18Kb", "36Kb" | "18Kb" | Configures FIFO as "18Kb" or "36Kb" memory. |
VHDL Instantiation Template
Unless
they already exist, copy the following four statements and paste them
before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
-- FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer
-- 7 Series
-- Xilinx HDL Language Template, version 2022.2
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
-----------------------------------------------------------------
-- DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width --
-- ===========|===========|============|=======================--
-- 37-72 | "36Kb" | 512 | 9-bit --
-- 19-36 | "36Kb" | 1024 | 10-bit --
-- 19-36 | "18Kb" | 512 | 9-bit --
-- 10-18 | "36Kb" | 2048 | 11-bit --
-- 10-18 | "18Kb" | 1024 | 10-bit --
-- 5-9 | "36Kb" | 4096 | 12-bit --
-- 5-9 | "18Kb" | 2048 | 11-bit --
-- 1-4 | "36Kb" | 8192 | 13-bit --
-- 1-4 | "18Kb" | 4096 | 12-bit --
-----------------------------------------------------------------
FIFO_SYNC_MACRO_inst : FIFO_SYNC_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5, "VIRTEX6", "7SERIES"
ALMOST_FULL_OFFSET => X"0080", -- Sets almost full threshold
ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold
DATA_WIDTH => 0, -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
FIFO_SIZE => "18Kb") -- Target BRAM, "18Kb" or "36Kb"
port map (
ALMOSTEMPTY => ALMOSTEMPTY, -- 1-bit output almost empty
ALMOSTFULL => ALMOSTFULL, -- 1-bit output almost full
DO => DO, -- Output data, width defined by DATA_WIDTH parameter
EMPTY => EMPTY, -- 1-bit output empty
FULL => FULL, -- 1-bit output full
RDCOUNT => RDCOUNT, -- Output read count, width determined by FIFO depth
RDERR => RDERR, -- 1-bit output read error
WRCOUNT => WRCOUNT, -- Output write count, width determined by FIFO depth
WRERR => WRERR, -- 1-bit output write error
CLK => CLK, -- 1-bit input clock
DI => DI, -- Input data, width defined by DATA_WIDTH parameter
RDEN => RDEN, -- 1-bit input read enable
RST => RST, -- 1-bit input reset
WREN => WREN -- 1-bit input write enable
);
-- End of FIFO_SYNC_MACRO_inst instantiation
Verilog Instantiation Template
// FIFO_SYNC_MACRO: Synchronous First-In, First-Out (FIFO) RAM Buffer
// 7 Series
// Xilinx HDL Language Template, version 2022.2
/////////////////////////////////////////////////////////////////
// DATA_WIDTH | FIFO_SIZE | FIFO Depth | RDCOUNT/WRCOUNT Width //
// ===========|===========|============|=======================//
// 37-72 | "36Kb" | 512 | 9-bit //
// 19-36 | "36Kb" | 1024 | 10-bit //
// 19-36 | "18Kb" | 512 | 9-bit //
// 10-18 | "36Kb" | 2048 | 11-bit //
// 10-18 | "18Kb" | 1024 | 10-bit //
// 5-9 | "36Kb" | 4096 | 12-bit //
// 5-9 | "18Kb" | 2048 | 11-bit //
// 1-4 | "36Kb" | 8192 | 13-bit //
// 1-4 | "18Kb" | 4096 | 12-bit //
/////////////////////////////////////////////////////////////////
FIFO_SYNC_MACRO #(
.DEVICE("7SERIES"), // Target Device: "7SERIES"
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
.DATA_WIDTH(0), // Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")
.DO_REG(0), // Optional output register (0 or 1)
.FIFO_SIZE ("18Kb") // Target BRAM: "18Kb" or "36Kb"
) FIFO_SYNC_MACRO_inst (
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit output almost empty
.ALMOSTFULL(ALMOSTFULL), // 1-bit output almost full
.DO(DO), // Output data, width defined by DATA_WIDTH parameter
.EMPTY(EMPTY), // 1-bit output empty
.FULL(FULL), // 1-bit output full
.RDCOUNT(RDCOUNT), // Output read count, width determined by FIFO depth
.RDERR(RDERR), // 1-bit output read error
.WRCOUNT(WRCOUNT), // Output write count, width determined by FIFO depth
.WRERR(WRERR), // 1-bit output write error
.CLK(CLK), // 1-bit input clock
.DI(DI), // Input data, width defined by DATA_WIDTH parameter
.RDEN(RDEN), // 1-bit input read enable
.RST(RST), // 1-bit input reset
.WREN(WREN) // 1-bit input write enable
);
// End of FIFO_SYNC_MACRO_inst instantiation