FIFO36E1 - 2022.2 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2022-10-19
Version
2022.2 English

Primitive: 36 Kb FIFO (First-In-First-Out) Block RAM Memory

Introduction

7 series devices contain several block RAM memories that can be configured as FIFOs, automatic error-correction RAM, or general-purpose 36 Kb or 18 Kb RAM/ROM memories. These Block RAM memories offer fast and flexible storage of large amounts of on-chip data. The FIFO36E1 allows access to the Block RAM in the 36 Kb FIFO configurations. This component can be configured and used as a 4-bit wide by 8K deep, 9-bit by 4K deep, 18-bit by 2K deep, 36-bit wide by 1K deep, or 72-bit wide by 512 deep synchronous or dual-clock (asynchronous) FIFO RAM with all associated FIFO flags.

When using the dual-clock mode with independent clocks, depending on the offset between read and write clock edges, the Empty, Almost Empty, Full and Almost Full flags can deassert one cycle later. Due to the asynchronous nature of the clocks the simulation model only reflects the deassertion latency cycles listed in the User Guide.

Note: For a 72-bit wide by 512 deep FIFO, the "FIFO36_72" mode must be used. For smaller configurations of the FIFO, the FIFO18E1 can be used. If error-correction circuitry is desired, the "FIFO36_72" mode must be used.

Port Descriptions

Port Direction Width Function
ALMOSTEMPTY Output 1 Programmable flag to indicate the FIFO is almost empty. The ALMOST_EMPTY_OFFSET attribute specifies where to trigger this flag.
ALMOSTFULL Output 1 Programmable flag to indicate the FIFO is almost full. The ALMOST_FULL_OFFSET attribute specifies where to trigger this flag.
DBITERR Output 1 Status output from ECC function to indicate a double bit error was detected. EN_ECC_READ needs to be TRUE to use this functionality.
DI<63:0> Input 64 FIFO data input bus.
DIP<7:0> Input 8 FIFO parity data input bus.
DO<63:0> Output 64 FIFO data output bus.
DOP<7:0> Output 8 FIFO parity data output bus.
ECCPARITY<7:0> Output 8 8-bit data generated by the ECC encoder used by the ECC decoder for memory error detection and correction.
EMPTY Output 1 Active-High logic to indicate that the FIFO is currently empty.
FULL Output 1 Active-High logic indicates that the FIFO is full.
INJECTDBITERR Input 1 Inject a double bit error if ECC feature is used.
INJECTSBITERR Input 1 Inject a single bit error if ECC feature is used.
RDCLK Input 1 Rising edge read clock.
RDCOUNT<12:0> Output 13 Read count.
RDEN Input 1 Active-High FIFO read enable.
RDERR Output 1 Read error occurred.
REGCE Input 1 Output register clock enable for pipelined synchronous FIFO. DO_REG must be 1 to use this enable.
RST Input 1 Active-High (FIFO logic) asynchronous reset (for dual-clock FIFO), synchronous reset (synchronous FIFO) for 5 CLK cycles.
RSTREG Input 1 Output register synchronous set/reset. DO_REG must be 1 to use this reset.
SBITERR Output 1 Status output from ECC function to indicate a single bit error was detected. EN_ECC_READ needs to be TRUE to use this functionality.
WRCLK Input 1 Write clock and enable input signals.
WRCOUNT<12:0> Output 13 Write count.
WREN Input 1 Active-High FIFO write enable.
WRERR Output 1 Write error occurred. When the FIFO is full, any additional write operation generates an error flag. Synchronous with WRCLK.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog Yes
Macro support Recommended

Available Attributes

Attribute Type Allowed Values Default Description
ALMOST_EMPTY _OFFSET HEX 13'h0000 to 13'h1fff 13'h0080 Specifies the amount of data contents in the RAM to trigger the ALMOST_EMPTY flag.
ALMOST_FULL _OFFSET HEX 13'h0000 to 13'h1fff 13'h0080 Specifies the amount of data contents in the RAM to trigger the ALMOST_FULL flag.
DATA_WIDTH DECIMAL 4, 9, 18, 36, 72 4 Specifies the desired data width for the FIFO. For data widths of 72, FIFO_MODE must be set to "FIFO36_72."
DO_REG DECIMAL 1, 0 1 Enable output register to the FIFO for improved clock-to-out timing at the expense of added read latency (one pipeline delay). DO_REG must be 1 when EN_SYN is set to FALSE.
EN_ECC_READ BOOLEAN FALSE, TRUE FALSE Enable the ECC decoder circuitry.
EN_ECC_WRITE BOOLEAN FALSE, TRUE FALSE Enable the ECC encoder circuitry.
EN_SYN BOOLEAN FALSE, TRUE FALSE When FALSE, specifies the FIFO to be used in asynchronous mode (two independent clock) or when TRUE in synchronous (a single clock) operation.
FIFO_MODE STRING "FIFO36", "FIFO36_72" "FIFO36" Selects regular "FIFO36" or the wide "FIFO36_72" mode. If set to "FIFO36_72", the DATA_WIDTH attribute has to be 72.
FIRST_WORD_FALL _THROUGH BOOLEAN FALSE, TRUE FALSE If TRUE, the first write to the FIFO will appear on DO without an RDEN assertion.
INIT HEX 72 bit HEX All zeros Specifies the initial value on the DO output after configuration.
SIM_DEVICE STRING "7SERIES" "7SERIES" Must be set to "7SERIES" to exhibit proper simulation behavior under all conditions.
SRVAL HEX 72 bit HEX All zeros Specifies the output value of the FIFO upon assertion of the synchronous reset (RSTREG) signal. Only valid for DO_REG=1.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- FIFO36E1: 36Kb FIFO (First-In-First-Out) Block RAM Memory
--           7 Series
-- Xilinx HDL Language Template, version 2022.2

FIFO36E1_inst : FIFO36E1
generic map (
   ALMOST_EMPTY_OFFSET => X"0080",   -- Sets the almost empty threshold
   ALMOST_FULL_OFFSET => X"0080",    -- Sets almost full threshold
   DATA_WIDTH => 4,                  -- Sets data width to 4-72
   DO_REG => 1,                      -- Enable output register (1-0) Must be 1 if EN_SYN = FALSE
   EN_ECC_READ => FALSE,             -- Enable ECC decoder, FALSE, TRUE
   EN_ECC_WRITE => FALSE,            -- Enable ECC encoder, FALSE, TRUE
   EN_SYN => FALSE,                  -- Specifies FIFO as Asynchronous (FALSE) or Synchronous (TRUE)
   FIFO_MODE => "FIFO36",            -- Sets mode to "FIFO36" or "FIFO36_72"
   FIRST_WORD_FALL_THROUGH => FALSE, -- Sets the FIFO FWFT to FALSE, TRUE
   INIT => X"000000000000000000",    -- Initial values on output port
   SIM_DEVICE => "7SERIES",          -- Must be set to "7SERIES" for simulation behavior
   SRVAL => X"000000000000000000"    -- Set/Reset value for output port
)
port map (
   -- ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
   DBITERR => DBITERR,             -- 1-bit output: Double bit error status
   ECCPARITY => ECCPARITY,         -- 8-bit output: Generated error correction parity
   SBITERR => SBITERR,             -- 1-bit output: Single bit error status
   -- Read Data: 64-bit (each) output: Read output data
   DO => DO,                       -- 64-bit output: Data output
   DOP => DOP,                     -- 8-bit output: Parity data output
   -- Status: 1-bit (each) output: Flags and other FIFO status outputs
   ALMOSTEMPTY => ALMOSTEMPTY,     -- 1-bit output: Almost empty flag
   ALMOSTFULL => ALMOSTFULL,       -- 1-bit output: Almost full flag
   EMPTY => EMPTY,                 -- 1-bit output: Empty flag
   FULL => FULL,                   -- 1-bit output: Full flag
   RDCOUNT => RDCOUNT,             -- 13-bit output: Read count
   RDERR => RDERR,                 -- 1-bit output: Read error
   WRCOUNT => WRCOUNT,             -- 13-bit output: Write count
   WRERR => WRERR,                 -- 1-bit output: Write error
   -- ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
   INJECTDBITERR => INJECTDBITERR, -- 1-bit input: Inject a double bit error input
   INJECTSBITERR => INJECTSBITERR,
   -- Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
   RDCLK => RDCLK,                 -- 1-bit input: Read clock
   RDEN => RDEN,                   -- 1-bit input: Read enable
   REGCE => REGCE,                 -- 1-bit input: Clock enable
   RST => RST,                     -- 1-bit input: Reset
   RSTREG => RSTREG,               -- 1-bit input: Output register set/reset
   -- Write Control Signals: 1-bit (each) input: Write clock and enable input signals
   WRCLK => WRCLK,                 -- 1-bit input: Rising edge write clock.
   WREN => WREN,                   -- 1-bit input: Write enable
   -- Write Data: 64-bit (each) input: Write input data
   DI => DI,                       -- 64-bit input: Data input
   DIP => DIP                      -- 8-bit input: Parity input
);

-- End of FIFO36E1_inst instantiation

Verilog Instantiation Template


// FIFO36E1: 36Kb FIFO (First-In-First-Out) Block RAM Memory
//           7 Series
// Xilinx HDL Language Template, version 2022.2

FIFO36E1 #(
   .ALMOST_EMPTY_OFFSET(13'h0080),    // Sets the almost empty threshold
   .ALMOST_FULL_OFFSET(13'h0080),     // Sets almost full threshold
   .DATA_WIDTH(4),                    // Sets data width to 4-72
   .DO_REG(1),                        // Enable output register (1-0) Must be 1 if EN_SYN = FALSE
   .EN_ECC_READ("FALSE"),             // Enable ECC decoder, FALSE, TRUE
   .EN_ECC_WRITE("FALSE"),            // Enable ECC encoder, FALSE, TRUE
   .EN_SYN("FALSE"),                  // Specifies FIFO as Asynchronous (FALSE) or Synchronous (TRUE)
   .FIFO_MODE("FIFO36"),              // Sets mode to "FIFO36" or "FIFO36_72"
   .FIRST_WORD_FALL_THROUGH("FALSE"), // Sets the FIFO FWFT to FALSE, TRUE
   .INIT(72'h000000000000000000),     // Initial values on output port
   .SIM_DEVICE("7SERIES"),            // Must be set to "7SERIES" for simulation behavior
   .SRVAL(72'h000000000000000000)     // Set/Reset value for output port
)
FIFO36E1_inst (
   // ECC Signals: 1-bit (each) output: Error Correction Circuitry ports
   .DBITERR(DBITERR),             // 1-bit output: Double bit error status
   .ECCPARITY(ECCPARITY),         // 8-bit output: Generated error correction parity
   .SBITERR(SBITERR),             // 1-bit output: Single bit error status
   // Read Data: 64-bit (each) output: Read output data
   .DO(DO),                       // 64-bit output: Data output
   .DOP(DOP),                     // 8-bit output: Parity data output
   // Status: 1-bit (each) output: Flags and other FIFO status outputs
   .ALMOSTEMPTY(ALMOSTEMPTY),     // 1-bit output: Almost empty flag
   .ALMOSTFULL(ALMOSTFULL),       // 1-bit output: Almost full flag
   .EMPTY(EMPTY),                 // 1-bit output: Empty flag
   .FULL(FULL),                   // 1-bit output: Full flag
   .RDCOUNT(RDCOUNT),             // 13-bit output: Read count
   .RDERR(RDERR),                 // 1-bit output: Read error
   .WRCOUNT(WRCOUNT),             // 13-bit output: Write count
   .WRERR(WRERR),                 // 1-bit output: Write error
   // ECC Signals: 1-bit (each) input: Error Correction Circuitry ports
   .INJECTDBITERR(INJECTDBITERR), // 1-bit input: Inject a double bit error input
   .INJECTSBITERR(INJECTSBITERR),
   // Read Control Signals: 1-bit (each) input: Read clock, enable and reset input signals
   .RDCLK(RDCLK),                 // 1-bit input: Read clock
   .RDEN(RDEN),                   // 1-bit input: Read enable
   .REGCE(REGCE),                 // 1-bit input: Clock enable
   .RST(RST),                     // 1-bit input: Reset
   .RSTREG(RSTREG),               // 1-bit input: Output register set/reset
   // Write Control Signals: 1-bit (each) input: Write clock and enable input signals
   .WRCLK(WRCLK),                 // 1-bit input: Rising edge write clock.
   .WREN(WREN),                   // 1-bit input: Write enable
   // Write Data: 64-bit (each) input: Write input data
   .DI(DI),                       // 64-bit input: Data input
   .DIP(DIP)                      // 8-bit input: Parity input
);

// End of FIFO36E1_inst instantiation

Related Information

  • See the 7 Series FPGAs Memory Resources User Guide (UG473).