Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
Introduction
This design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the (Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on the Low-to-High clock (C) transition. When CE is Low, the clock transitions are ignored.
This flip-flop is asynchronously preset, outputs High, when power is applied. Power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_E2 symbol.
Logic Table
Inputs | Outputs | |||
---|---|---|---|---|
PRE | CE | D | C | Q |
1 | X | X | X | 1 |
0 | 0 | X | X | No Change |
0 | 1 | D | ↑ | D |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | BINARY | 0, 1 | 1 | Sets the initial value of Q output after configuration. |
VHDL Instantiation Template
Library UNISIM;
use UNISIM.vcomponents.all;
-- FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
-- Clock Enable (posedge clk).
-- 7 Series
-- Xilinx HDL Language Template, version 2022.2
FDPE_inst : FDPE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
PRE => PRE, -- Asynchronous preset input
D => D -- Data input
);
-- End of FDPE_inst instantiation
Verilog Instantiation Template
// FDPE: Single Data Rate D Flip-Flop with Asynchronous Preset and
// Clock Enable (posedge clk).
// 7 Series
// Xilinx HDL Language Template, version 2022.2
FDPE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDPE_inst (
.Q(Q), // 1-bit Data output
.C(C), // 1-bit Clock input
.CE(CE), // 1-bit Clock enable input
.PRE(PRE), // 1-bit Asynchronous preset input
.D(D) // 1-bit Data input
);
// End of FDPE_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).