Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear
Introduction
This design element is a single D-type flip-flop with clock enable and asynchronous clear.
- When clock enable (CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of this design element is transferred to the corresponding data output (Q) during the Low-to-High clock (C) transition.
- When CLR is High, it overrides all other inputs and resets the data output (Q) Low.
- When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. Power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_E2 symbol.
Logic Table
Inputs | Outputs | |||
---|---|---|---|---|
CLR | CE | D | C | Q |
1 | X | X | X | 0 |
0 | 0 | X | X | No Change |
0 | 1 | D | ↑ | D |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP Catalog | No |
Macro support | No |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
INIT | BINARY | 1, 0 | 0 | Sets the initial value of Q output after configuration. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
-- Clock Enable (posedge clk).
-- 7 Series
-- Xilinx HDL Language Template, version 2022.2
FDCE_inst : FDCE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
CLR => CLR, -- Asynchronous clear input
D => D -- Data input
);
-- End of FDCE_inst instantiation
Verilog Instantiation Template
// FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
// Clock Enable (posedge clk).
// 7 Series
// Xilinx HDL Language Template, version 2022.2
FDCE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDCE_inst (
.Q(Q), // 1-bit Data output
.C(C), // 1-bit Clock input
.CE(CE), // 1-bit Clock enable input
.CLR(CLR), // 1-bit Asynchronous clear input
.D(D) // 1-bit Data input
);
// End of FDCE_inst instantiation
Related Information
- See the 7 Series FPGAs Configurable Logic Block User Guide (UG474).