BUFHCE - 2022.2 English

Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2022-10-19
Version
2022.2 English

Primitive: HROW Clock Buffer for a Single Clocking Region with Clock Enable

Introduction

The BUFHCE primitive allows direct access to the clock region entry point of the global buffer (BUFG) resource. This allows access to unused portions of the global clocking network to be used as high-speed, low skew local (single clock region) routing resources. Additionally, the clock enable input (CE) allows for finer-grained control of clock enabling or gating to allow for power reduction for circuitry or portions of the design not constantly used.

Port Descriptions

Port Direction Width Function
CE Input 1 Enables propagation of signal from I to O. When low, performs a glitchless transition of the output to INIT_OUT value.
I Input 1 Clock input.
O Output 1 Clock output.

Design Entry Method

Instantiation Yes
Inference No
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
CE_TYPE STRING "SYNC", "ASYNC" "SYNC" Sets clock enable behavior where "SYNC" allows for a glitchless transition to and from the INIT_OUT value. "ASYNC" is generally used to create a more immediate transition such as when you can expect the clock to be stopped or when using the BUFHCE for a high fanout control or data path routing instead of a clock buffer.
INIT_OUT DECIMAL 0, 1 0 Initial output value, also indicates stop low vs. stop high behavior.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
--         7 Series
-- Xilinx HDL Language Template, version 2022.2

BUFHCE_inst : BUFHCE
generic map (
   CE_TYPE => "SYNC", -- "SYNC" (glitchless switching) or "ASYNC" (immediate switch)
   INIT_OUT => 0      -- Initial output value (0-1)
)
port map (
   O => O,   -- 1-bit output: Clock output
   CE => CE, -- 1-bit input: Active high enable
   I => I    -- 1-bit input: Clock input
);

-- End of BUFHCE_inst instantiation

Verilog Instantiation Template


// BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
//         7 Series
// Xilinx HDL Language Template, version 2022.2

BUFHCE #(
   .CE_TYPE("SYNC"), // "SYNC" (glitchless switching) or "ASYNC" (immediate switch)
   .INIT_OUT(0)      // Initial output value (0-1)
)
BUFHCE_inst (
   .O(O),   // 1-bit output: Clock output
   .CE(CE), // 1-bit input: Active high enable
   .I(I)    // 1-bit input: Clock input
);

// End of BUFHCE_inst instantiation

Related Information

  • See the 7 Series FPGAs Clocking Resource User Guide (UG472).