Viewing Hierarchical Signal Names - 2022.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)
Document ID
UG937
Release Date
2022-12-23
Version
2022.2 English
By default, the Vivado® simulator adds signals to the waveform configuration using a short name with the hierarchy reference removed. For some signals, it is important to know to which module they belong.
  1. In the Waveform window, hold Ctrl and click to select the sine[19:0] and sineSel[1:0] signals listed in the DUT signals group, under the SineGen divider.
  2. Hold Ctrl, and click to select the sine[19:0] signals listed in the Outputs group, under the SineGen divider.
  3. Right-click in the Waveform window to open the popup menu, and select the Name > Long command.

    The displayed name changes to include the hierarchical path of the signal. You can now see that the sine[19:0] signals under the DUT Signals group refers to different objects in the design hierarchy than the sine[19:0] signals listed under the Outputs group. See the figure below.