Step 10: Relaunch Simulation - 2022.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2022-12-23
Version
2022.2 English
By using breakpoints and line stepping, you identified the problem with the low frequency output of the design and corrected it.

Because you modified the source files associated with the design, you must recompile the HDL source and build new simulation snapshot. Do not just restart the simulation at time 0 in this case but rebuild the simulation from scratch.

  1. In sinegen.vhd, select one of the breakpoints, right-click and select Delete All Breakpoints.
  2. Click the Relaunch button on the main toolbar menu.
    Note: If prompted to save the Wave Config file, click yes.

    The Vivado® simulator recompiles the source files with xelab, and re-creates the simulation snapshot. Now you are ready to simulate with the corrected design files. The relaunch button will be active only after one successful run of Vivado Simulator using launch_simulation. If you run the simulation in a Batch/Scripted mode, the relaunch button would be greyed out.

  3. Click the Run All button to run the simulation.

    Observe the sine[19:0], the analog signal in the waveform configuration. The low frequency sine wave looks as expected. The Tcl console results are:

    [@3518000] LEDS_n = 0100
    [@3523000] LEDS_n = 0001
    [@3523000] LEDS_n = 0001
    [@6008000] LEDS_n = 0101
    [@6013000] LEDS_n = 0010
    [@6013000] LEDS_n = 0010
    $finish called at time : 7005 ns : File "ug937/sim/testbench.v" Line 63