In this lab, you create a new Vivado® Design Suite project, add HDL design sources, add IP from the Xilinx® IP catalog, and generate IP outputs needed for simulation. Then you run a behavioral simulation on an elaborated RTL design.
In this lab, you create a new Vivado® Design Suite project, add HDL design sources, add IP from the Xilinx® IP catalog, and generate IP outputs needed for simulation. Then you run a behavioral simulation on an elaborated RTL design.