Creating an Example Design - 2022.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)
Document ID
UG937
Release Date
2022-12-23
Version
2022.2 English
You will now generate an AXI-VIP example design.
  1. Open Vivado® .
  2. Create a project with the name mySystemVerilog by invoking the following command in Vivado Tcl Console.
    create_project mySystemVerilog ./mySystemVerilog


  3. You will create an AXI-VIP example design that includes the following features:
    • Random Constraint
    • Dynamic Types and Class
    • Virtual Interface
    • Assertion
    • Clocking Block
  4. Invoke the following commands in Tcl Console:
    1. create_ip -name axi_vip -vendor xilinx.com -library ip -version 1.1 -module_name axi_vip_0
    2. open_example_project -force [get_ips axi_vip_0]
Now you have created an example design for AXI-VIP with the name axi_vip_0_ex.