Adding Sine Low - 2022.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)
Document ID
UG937
Release Date
2022-12-23
Version
2022.2 English
  1. In the IP catalog, double-click the DDS Compiler IP for the third time.
  2. Specify the following on the Configuration tab:
    • Component Name: type sine_low
    • Configuration Options: select SIN COS LUT only
    • Noise Shaping: select None
    • Under Hardware Parameters, set the Phase Width to 6 and the Output Width to 16
  3. On the Implementation tab, set the Output Selection to Sine.
  4. On the Detailed Implementation tab, set Control Signals to ARESETn (active-Low).
  5. Select the Summary tab, review the settings as seen in the following figure, and click OK.

    When the sine_low IP core is added to the design, the Generate Output Products dialog box displays to generate the output products required to support the IP in the design.

  6. Click Generate to generate the default output products for sine_low. A dialog box opens saying that the Out of context module run was launched for generating output products. Click OK.