Adding Sine High - 2022.2 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2022-12-23
Version
2022.2 English
  1. In the Flow Navigator, select the IP Catalog button.

    The IP catalog opens in the graphical windows area. For more information on the specifics of the Vivado® IDE, refer to the Vivado Design Suite User Guide: Using the Vivado IDE (UG893).

  2. In the Search field of the IP catalog, type DDS.

    The Vivado IDE highlights the DDS Compilers in the IP catalog.

  3. Under any category, double-click the DDS Compiler.

    The Customize IP wizard opens as shown in the following figure:



  4. In the IP Symbol tab on the left, ensure that Show disabled ports is unchecked.
  5. Specify the following on the Configuration tab:
    • Component Name: type sine_high
    • Configuration Options: select SIN COS LUT only
    • Noise Shaping: select None
    • Under Hardware Parameters, set Phase Width to 16 and Output Width to 20
  6. On the Implementation tab, set Output Selection to Sine.
  7. On the Detailed Implementation tab, set Control Signals to ARESETn (active-Low).
  8. On the Summary tab, review the settings and click OK.

    When the sine_high IP core is added to the design, the output products required to support the IP in the design must be generated. The Generate Output Products dialog box displays, as shown in the following figure.



    The output products allow the IP to be synthesized, simulated, and implemented as part of the design. For more information on working with IP cores and the Xilinx® IP catalog, refer to the Vivado Design Suite User Guide: Designing with IP (UG896). You can also work through the Vivado Design Suite Tutorial: Designing with IP (UG939).

  9. Click Generate to generate the default output products for sine_high. A dialog box opens saying that the Out of context module run was launched for generating output products. Click OK.