Vivado Design Suite Tutorial: Logic Simulation (UG937) - 2022.2 English

Document ID: UG937
Release Date: 2022-12-23
Version: 2022.2 English

Vivado Simulator Overview
Introduction
Tutorial Description
Locating Tutorial Design Files
Software and Hardware Requirements
Lab 1: Running the Simulator in Vivado IDE
Step 1: Creating a New Project
Step 2: Adding IP from the IP Catalog
Adding Sine High
Adding Sine Mid
Adding Sine Low
Step 3: Running Behavioral Simulation
Conclusion
Lab 2: Debugging the Design
Step 1: Opening the Project
Step 2: Displaying Signal Waveforms
Add and Monitor Signals
Step 3: Using the Analog Wave Viewer
Logging Waveforms for Debugging
Using the Tcl Command
Step 4: Working with the Waveform Window
Grouping Signals
Adding Dividers
Adding Signals from Sub-modules
Step 5: Changing Signal Properties
Viewing Hierarchical Signal Names
Viewing Signal Values
Step 6: Saving the Waveform Configuration
Working with Multiple Waveform Configurations
Step 7: Re-Simulating the Design
Step 8: Using Cursors, Markers, and Measuring Time
Step 9: Debugging with Breakpoints
Using Breakpoints
Stepping Through Source Code
Step 10: Relaunch Simulation
Conclusion
Lab 3: Running Simulation in Batch Mode
Step 1: Preparing the Simulation
Creating the Vivado Simulator Project File
Manually Parsing Design Files
Step 2: Building the Simulation Snapshot
Running xelab
Step 3: Manually Simulating the Design
Conclusion
Lab 4: System Verilog Feature
Creating an Example Design
Launching Simulation
Debugging Using Vivado Simulator
Scope Window
Object Window
Tcl Console
Functional Coverage
Cover Group Declaration
Assertion
Immediate Assertion
Concurrent Assertion
Random Constraint
Lab 5: Running UVM example
Creating a New Project
Lab 6: Running GTM-Wizard example
Overview
Feature Covered
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
Revision History
Please Read: Important Legal Notices

Back to home page