Vivado Design Suite Tutorial: Programming and Debugging (UG936) - 2022.2 English - Describes debugging Xilinx® FPGA designs using the Integrated Logic Analyzer (ILA) core in the Vivado® Design Suite and the Vivado logic analyzer to debug common problems in FPGA logic designs. Uses the Vivado logic analyzer in real-time and a KC705 Evaluation Board featuring a Kintex®-7 device. - UG936

Document ID

UG936

Release Date

2022-11-16

Version

2022.2 English