CLOCK_BUFFER_TYPE - 2022.2 English - UG912

Vivado Design Suite Properties Reference Guide (UG912)
Document ID
UG912
Release Date
2022-11-02
Version
2022.2 English

By default, Vivado synthesis infers an input buffer and global clock buffer (IBUF/BUFG) combination for clocks ports. However, you can use the IO_BUFFER_TYPE and the CLOCK_BUFFER_TYPE properties together to direct the Vivado synthesis tool to change the default buffer types, such as an IBUF/BUFR pair, or no input buffer with a BUFIO clock buffer; or to eliminate the buffers altogether.

Mandatory logic optimization (MLO), which occurs at the beginning of link_design and opt_design supports the use of the CLOCK_BUFFER_TYPE property to insert global clock buffers. Supported values are BUFG for 7 series, and BUFG and BUFGCE for UltraScale, UltraScale+, and Versal devices. The value NONE can be used for all architectures to suppress global clock buffer insertion through MLO and opt_design. For the values BUFG and BUFGCE, opt_design and MLO inserts the corresponding buffer type to drive the specified net.

The CLOCK_BUFFER_TYPE property indicates what type of clock buffer to infer for the specified net or port objects. The IO_BUFFER_TYPE property indicates whether to infer an input or output buffer for the port.

Tip: The use of the CLOCK_BUFFER_TYPE property implies a KEEP on the target net, which preserves the net name and prevents removing the net through RTL optimization.

CLOCK_BUFFER_TYPE can be defined in the RTL or in the XDC. When specified in the RTL, the property can be attached to a port. After synthesis, the property CLOCK_BUFFER_TYPE should be attached to the net driven by the input buffer.

Note: MAX_FANOUT does not work on nets with CLOCK_BUFFER_TYPE.

Applicable Objects

Ports (get_ports)
Apply CLOCK_BUFFER_TYPE to any top-level clock port to describe what type of clock buffer to use, or to use no clock buffer. For 7 series, UltraScale and Ultra Scale Plus, the property can only be set on ports inside RTL and will not be used by opt_design when set on ports through XDC. For Versal ACAP, opt_design only supports CLOCK_BUFFER_TYPE on ports through XDC for OOC implementation. For any other flow, the property should be set on the net driven by the top-level port.
Nets (get_nets)
Apply CLOCK_BUFFER_TYPE to any signal connected to a top-level clock port (synthesis) or any net (logic optimization) to describe what type of clock buffer to use, or to use no clock buffer.

Value

  • BUFGCE, BUFG, BUFH, BUFIO, BUFMR, BUFR: Directs the tool to infer the specified clock buffer for clock ports or nets.
  • NONE: Directs the tool to not infer any clock buffers for the clocks.
    Note: Use with IO_BUFFER_TYPE “NONE” to prevent Vivado synthesis from inferring any buffers.

Syntax

Verilog Syntax
(* clock_buffer_type = "none" *) input clk1;
VHDL Syntax
entity test is port(
in1 : std_logic_vector (8 downto 0); clk : std_logic;
out1 : std_logic_vector(8 downto 0)); attribute clock_buffer_type : string;
attribute clock_buffer_type of clk: signal is "BUFR"; end test;
XDC Syntax
set_property CLOCK_BUFFER_TYPE BUFMR [get_nets <net_name>]

Affected Steps

  • Synthesis
  • Opt Design
Related reference