UCF to XDC Mapping - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

For information, see the following guides:

Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 3]

Vivado Design Suite Tcl Command Reference Guide (UG835) [Ref 4]

Vivado Design Suite Properties Reference Guide (UG912) [Ref 13]

Table:  UCF to XDC Mapping shows the main mapping between UCF constraints to XDC commands.

Table 3-1: UCF to XDC Mapping

UCF

XDC

TIMESPEC PERIOD

create_clock

create_generated_clock

OFFSET = IN <x> BEFORE <clk>

set_input_delay

OFFSET = OUT <x> BEFORE <clk>

set_output_delay

FROM:TO “TS_”*2

set_multicycle_path

FROM:TO

set_max_delay

TIG

set_false_path

NET “clk_p” LOC = AD12

set_property LOC AD12 [get_ports clk_p]

NET “clk_p” IOSTANDARD = LVDS

set_property IOSTANDARD LVDS [get_ports clk_p]