Setting AXI Slave(s) Register Slicing and AXI Data FIFO - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

1. Open the MHS file, and for each AXI slave set the Enable Register Slice/Enable Data FIFO, based upon searching the MHS in the Table: AXI Slave Interconnect Settings with MicroBlaze Devices .

When doing the search, replace <intf_name> with the associated BUS_INTERFACE name. For example, <intf_name> for BUS_INTERFACE S_AXI would be S_AXI .

TIP: AXI Slaves connect to the AXI Interconnect Master connection. You can make the selection in the Master Interfaces tab.

Table 5-8: AXI Slave Interconnect Settings with MicroBlaze Devices

Parameter

Exists

Does Not Exist

C_INTERCONNECT_<intf_name>_AR_REGISTER

C_INTERCONNECT_<intf_name>_R_REGISTER

C_INTERCONNECT_<intf_name>_AW_REGISTER

C_INTERCONNECT_<intf_name>_W_REGISTER

C_INTERCONNECT_<intf_name>_B_REGISTER

MXX_AXI: Enable Register Slice Auto

MXX_AXI : Enable Register Slice None

C_INTERCONNECT_<intf_name>_WRITE_FIFO_DEPTH

C_INTERCONNECT_<intf_name>_READ_FIFO_DEPTH

Parameter = 32

MXX_AXI: Enable Data FIFO 32 deep

Parameter = 512

MXX_AXI: Enable Data FIFO 512 deep

MXX_AXI : Enable Data FIFO None