RECOMMENDED: In the ISE Design Suite, OFFSET = OUT performs only maximum delay analysis. In the Vivado Design Suite, set_output_delay performs both maximum and minimum delay analysis. To constrain output ports in XDC files, Xilinx recommends using set_output_delay with the -max and -min options.
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AFTER |
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UCF Example |
OFFSET = OUT 12 AFTER clkc; |
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XDC Example |
set_output_delay -clock clkc -max 8 [all_outputs] Note: This assumes the clock period is 20 ns. |
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BEFORE |
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UCF Example |
OFFSET = OUT 8 BEFORE clkc; |
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XDC Example |
set_output_delay -clock clkc 8 [all_outputs] Note: This assumes the clock period is 20 ns. |
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Output Net |
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|---|---|
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UCF Example |
NET out_net OFFSET = OUT 12 AFTER clkc; |
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XDC Example |
set_output_delay 8 [get_port out_net] Note: This assumes the clock period is 20 ns. |
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Group of Outputs |
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|---|---|
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UCF Example |
TIMEGRP outputs OFFSET = OUT 12 AFTER clkc; |
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XDC Example |
set_output_delay -clock clkc 8 [get_ports outputs*] Note: This assumes the clock period is 20 ns. |
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From a TIMEGROUP |
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|---|---|
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UCF Example |
OFFSET = OUT 1.2 AFTER clk TIMEGRP from_ffs; |
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XDC Example |
Manual conversion is required. |
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FALLING/RISING Edges |
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|---|---|
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UCF Example |
OFFSET = OUT 12 AFTER clkc FALLING; |
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XDC Example |
set_output_delay -clock clkc -clock_fall 8 [all_outputs] |
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LOW Keyword |
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|---|---|
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UCF Example |
OFFSET = OUT 12 AFTER clkc LOW; |
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XDC Example |
Requires manual conversion. Note: HIGH/LOW keywords are precursors to RISING/FALLING. RISING/FALLING is the preferred method. |
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REFERENCE_PIN |
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|---|---|
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UCF Example |
TIMEGRP mac_ddr_out; OFFSET = OUT AFTER clk REFERENCE_PIN clk_out RISING; |
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XDC Example |
Requires manual conversion. Note: REFERENCE_PIN acts as a reporting switch to instruct TRACE to output a bus skew report. The Vivado Design Suite does not support this feature. |