OFFSET OUT - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

RECOMMENDED: In the ISE Design Suite, OFFSET = OUT performs only maximum delay analysis. In the Vivado Design Suite, set_output_delay performs both maximum and minimum delay analysis. To constrain output ports in XDC files, Xilinx recommends using set_output_delay with the -max and -min options.

AFTER

UCF Example

OFFSET = OUT 12 AFTER clkc;

XDC Example

set_output_delay -clock clkc -max 8 [all_outputs]

Note: This assumes the clock period is 20 ns.

BEFORE

UCF Example

OFFSET = OUT 8 BEFORE clkc;

XDC Example

set_output_delay -clock clkc 8 [all_outputs]

Note: This assumes the clock period is 20 ns.

Output Net

UCF Example

NET out_net OFFSET = OUT 12 AFTER clkc;

XDC Example

set_output_delay 8 [get_port out_net]

Note: This assumes the clock period is 20 ns.

Group of Outputs

UCF Example

TIMEGRP outputs OFFSET = OUT 12 AFTER clkc;

XDC Example

set_output_delay -clock clkc 8 [get_ports outputs*]

Note: This assumes the clock period is 20 ns.

From a TIMEGROUP

UCF Example

OFFSET = OUT 1.2 AFTER clk TIMEGRP from_ffs;

XDC Example

Manual conversion is required.

.

FALLING/RISING Edges

UCF Example

OFFSET = OUT 12 AFTER clkc FALLING;

XDC Example

set_output_delay -clock clkc -clock_fall 8 [all_outputs]

LOW Keyword

UCF Example

OFFSET = OUT 12 AFTER clkc LOW;

XDC Example

Requires manual conversion.

Note: HIGH/LOW keywords are precursors to RISING/FALLING. RISING/FALLING is the preferred method.

REFERENCE_PIN

UCF Example

TIMEGRP mac_ddr_out;

OFFSET = OUT AFTER clk REFERENCE_PIN clk_out RISING;

XDC Example

Requires manual conversion.

Note: REFERENCE_PIN acts as a reporting switch to instruct TRACE to output a bus skew report. The Vivado Design Suite does not support this feature.