The Vivado IDE uses the IP integrator tool for embedded development. A variety of IP are available in the Vivado IDE IP catalog to accommodate complex designs. You can also add custom IP to the IP catalog.
You can migrate a Zynq-7000 platform processor-based design into the Vivado Design Suite using the following steps.
1.
Generate the system infrastructure.
a.
Create a Vivado project with the desired board or programmable device.
b.
In the Flow Navigator, click
IP Integrator
and select
Create Block Design
.
c.
Enter the Design name:
design_1
. This generates the block design.
2.
Add the ZYNQ7 processing system and import the XML file from the XPS design.
a.
In the block diagram, right-click anywhere and select
Add IP
to open the IP Catalog.
b.
In the IP catalog, double-click
ZYNQ7 Processing System.
This instantiates a
processing_system7_0
instance on the block design.
c.
Double-click the
processing_system7_0
instance.
d.
At the top of the
Re-customize IP
dialog box, click
Import XPS Settings
.
e.
Click
browse
and select the directory of the XML file that was used for XPS.
f.
Click
OK
.
TIP:
Typically the XML file is located in the
<XPS_Project>/data/ps7_system_prj.xml
. The XML file stores information dealing with Zynq device Peripherals, MIO settings, DDR settings, and clocking including fabric clocks. You must enable AXI and other interfaces for Zynq devices manually.
3.
Open the MHS file and look at the
processing_system7
instance parameters and ports.
a.
In the Page Navigator, select the
PS-PL Configuration
.
b.
Do a search in the MHS file and set the following options based on the options listed in
Table: PS/PL Configuration Options Settings
.
Table 5-2:
PS/PL Configuration Options Settings
|
Parameter or Port
|
Exists
|
Does Not Exist
|
|
C_USE_M_AXI_GP0 = 1
|
GP Master AXI Interface/M AXI GP0 Interface:
Selected
|
GP Master AXI Interface/M AXI GP0 Interface:
Unselected
|
|
C_USE_M_AXI_GP1 = 1
|
GP Master AXI Interface/M AXI GP1 Interface:
Selected
|
GP Master AXI Interface/M AXI GP1 Interface:
Unselected
|
|
C_USE_S_AXI_GP0 = 1
|
GP Slave AXI Interface/S AXI GP0 Interface:
Selected
|
GP Slave AXI Interface/S AXI GP0 Interface:
Unselected
|
|
C_USE_S_AXI_GP1 = 1
|
GP Slave AXI Interface/S AXI GP1 Interface:
Selected
|
GP Slave AXI Interface/S AXI GP1 Interface:
Unselected
|
|
C_USE_S_AXI_HP0 = 1
|
HP Slave AXI Interface/S AXI HP0 Interface:
Selected
|
HP Slave AXI Interface/S AXI HP0 Interface:
Unselected
|
|
C_USE_S_AXI_HP1 = 1
|
HP Slave AXI Interface/S AXI HP1 Interface:
Selected
|
HP Slave AXI Interface/S AXI HP1 Interface:
Unselected
|
|
C_USE_S_AXI_HP2 = 1
|
HP Slave AXI Interface/S AXI HP2 Interface:
Selected
|
HP Slave AXI Interface/S AXI HP2 Interface:
Unselected
|
|
C_USE_S_AXI_HP3 = 1
|
HP Slave AXI Interface/S AXI HP3 Interface:
Selected
|
HP Slave AXI Interface/S AXI HP3 Interface:
Unselected
|
|
C_USE_S_AXI_ACP = 1
|
ACP Slave AXI Interface/S AXI ACP Interface:
Selected
|
ACP Slave AXI Interface/S AXI ACP Interface:
Unselected
|
|
FCLK_CLKTRIG0_N
|
General/Enable Clock
Triggers/FLCK_CLKTRIG0:
Selected
|
General/Enable Clock
Triggers/FLCK_CLKTRIG0:
Unselected
|
|
FCLK_CLKTRIG1_N
|
General/Enable Clock
Triggers/FLCK_CLKTRIG1:
Selected
|
General/Enable Clock
Triggers/FLCK_CLKTRIG1:
Unselected
|
|
FCLK_CLKTRIG2_N
|
General/Enable Clock Triggers/FLCK_CLKTRIG2:
Selected
|
General/Enable Clock Triggers/FLCK_CLKTRIG2:
Unselected
|
|
FCLK_CLKTRIG3_N
|
General/Enable Clock Triggers/FLCK_CLKTRIG3:
Selected
|
General/Enable Clock
Triggers/FLCK_CLKTRIG3:
Unselected
|
|
FCLK_RESET0_N
|
General/Enable Clock Resets/FCLK_RESET0_N:
Selected
|
General/Enable Clock Resets/FCLK_RESET0_N:
Unselected
|
|
FCLK_RESET1_N
|
General/Enable Clock
Resets/FCLK_RESET1_N:
Selected
|
General/Enable Clock
Resets/FCLK_RESET1_N:
Unselected
|
4.
In the Page Navigator, select
Clock Configuration
. Search the MHS file and set the following options based on the selections in
Table: CLock Configurations
.
The
Requested Frequencies
are set automatically based upon the imported XML file.
Table 5-3:
CLock Configurations
|
Port
|
Exists
|
Does Not Exist
|
|
FCLK_CLK0
|
PL Fabric
Clocks/FCLK_CLK0:
Selected
|
PL Fabric
Clocks/FCLK_CLK0:
Unselected
|
|
FCLK_CLK1
|
PL Fabric
Clocks/FCLK_CLK1:
Selected
|
PL Fabric
Clocks/FCLK_CLK1:
Unselected
|
|
FCLK_CLK2
|
PL Fabric
Clocks/FCLK_CLK2:
Selected
|
PL Fabric
Clocks/FCLK_CLK2:
Unselected
|
|
FCLK_CLK3
|
PL Fabric
Clocks/FCLK_CLK3:
Selected
|
PL Fabric
Clocks/FCLK_CLK3:
Unselected
|
5.
If interrupts are used:
a.
In the Page Navigator, select
Interrupts
.
b.
Check
Fabric Interrupts
and select the interrupts used by the Zynq device.
With BSB designs,
IRQ_F2P[15:0]
under PL-PS Interrupts Ports were used. Check
IRQ_F2P[15:0]
under PL-PS Interrupt Ports.
6.
In the Re-customize IP dialog box, click
OK
to save the imported settings.