IOB |
|
---|---|
Applied To |
Port nets |
Constraint Values |
IOB site |
UCF Example |
NET p[0] LOC = H1; |
XDC Example |
set_property PACKAGE_PIN H1 [get_ports p[0]] |
TIP: To assign pins in the Vivado Design Suite, use the PACKAGE_PIN port property, and not the LOC property, which is used for cells.
SLICE (1) |
|
---|---|
Applied To |
Cells |
Constraint Values |
Site range |
UCF Example |
INST a_reg[*] LOC = SLICE_X25Y*; |
XDC Example |
The Vivado Design Suite does not support this constraint in XDC. |
SLICE (2) |
|
---|---|
Applied To |
Cells |
Constraint Values |
SLICE_XnYn |
UCF Example |
INST a_reg[0] LOC = SLICE_X4Y4; |
XDC Example |
set_property LOC SLICE_X4Y4 [get_cells a_reg[0]] |
RAMB18 |
|
---|---|
Applied To |
Cells |
Constraint Values |
RAMB18_XnYn |
UCF Example |
INST ram0 LOC = RAMB18_X0Y5; |
XDC Example |
set_property LOC RAMB18_X0Y5 [get_cells ram0] |
RAMB36 |
|
---|---|
Applied To |
Cells |
Constraint Values |
RAMB36_XnYn |
UCF Example |
INST ram0 LOC = RAMB36_X0Y0; |
XDC Example |
set_property LOC RAMB36_X0Y0 [get_cells ram0] |
DSP48 |
|
---|---|
Applied To |
Cells |
Constraint Values |
DSP48_XnYn |
UCF Example |
INST dsp0 LOC = DSP48_X0Y10; |
XDC Example |
set_property LOC DSP48_X0Y10 [get_cells dsp0] |
BUFGCTRL |
|
---|---|
Applied To |
Cells |
Constraint Values |
BUFGCTRL_XnYn |
UCF Example |
INST cb[0] LOC = BUFGCTRL_X0Y24; |
XDC Example |
set_property LOC BUFGCTRL_X0Y24 [get_cells cb[0]] |
BUFHCE |
|
---|---|
Applied To |
Cells |
Constraint Values |
BUFHCE_XnYn |
UCF Example |
INST cb[0] LOC = BUFHCE_X0Y72; |
XDC Example |
set_property LOC BUFHCE_X0Y72 [get_cells cb[0]] |
BUFR |
|
---|---|
Applied To |
Cells |
Constraint Values |
BUFR_XnYn |
UCF Example |
INST cb[0] LOC = BUFR_X0Y20; |
XDC Example |
set_property LOC BUFR_X0Y20 [get_cells cb[0]] |
BUFIO |
|
---|---|
Applied To |
Cells |
Constraint Values |
BUFIO_XnYn |
UCF Example |
INST cb[0] LOC = BUFIO_X0Y8; |
XDC Example |
set_property LOC BUFIO_X0Y8 [get_cells cb[0]] |
KEEP_HIERARCHY |
|
---|---|
Applied To |
Cells |
Constraint Values |
• TRUE • FALSE • YES • NO |
UCF Example |
INST u1 KEEP_HIERARCHY = TRUE; |
XDC Example |
set_property DONT_TOUCH true [get_cells u1] |
IOB |
|
---|---|
Applied To |
Cells |
Constraint Values |
IOB_XnYn |
UCF Example |
INST ib[0] LOC = IOB_X0Y341; |
XDC Example |
set_property LOC IOB_X0Y341 [get_cells ib[0]] |
IN_FIFO |
|
---|---|
Applied To |
Cells |
Constraint Values |
IN_FIFO_XnYn |
UCF Example |
INST infifo_inst LOC = IN_FIFO_X0Y24; |
XDC Example |
set_property LOC IN_FIFO_X0Y24 [get_cells infifo_inst] |
OUT_FIFO |
|
---|---|
Applied To |
Cells |
Constraint Values |
OUT_FIFO_XnYn |
UCF Example |
INST outfifo_inst LOC = OUT_FIFO_X0Y24; |
XDC Example |
set_property LOC OUT_FIFO_X0Y24 [get_cells outfifo_inst] |
ILOGIC |
|
---|---|
Applied To |
Cells |
Constraint Values |
ILOGIC_XnYn |
UCF Example |
INST ireg LOC = ILOGIC_X0Y76; |
XDC Example |
set_property LOC ILOGIC_X0Y76 [get_cells ireg] |
OLOGIC |
|
---|---|
Applied To |
Cells |
Constraint Values |
OLOGIC_XnYn |
UCF Example |
INST oreg LOC = OLOGIC_X0Y76 |
XDC Example |
set_property LOC OLOGIC_X0Y76 [get_cells oreg] |
IDELAY |
|
---|---|
Applied To |
Cells |
Constraint Values |
IDELAY_XnYn |
UCF Example |
INST idelay0 LOC = IDELAY_X0Y21; |
XDC Example |
set_property LOC IDELAY_X0Y21 [get_cells idelay0] |
IDELAYCTRL |
|
---|---|
Applied To |
Cells |
Constraint Values |
IDELAYCTRL_XnYn |
UCF Example |
INST idelayctrl0 LOC = IDELAYCTRL_X0Y0; |
XDC Example |
set_property LOC IDELAYCTRL_X0Y0 [get_cells idelayctrl0] |