Feature
|
XPS
|
IP Integrator
|
IP catalog
|
Embedded-only IP catalog, which is separate from other Xilinx IP (CORE Generator
™
catalog)
|
Integrated Vivado Design Suite catalog
|
Design capture format
|
•
XMP file for project information (device, flow)
•
MHS file for design information (IPs and their connections)
|
•
Project information stored as part of design in the Vivado Design Suite
•
Design information stored in BD (XML format)
|
Text-based editing
|
MHS file editing in text editor/XPS editor
|
Tcl-based edit/design creation facilities in-line with the Vivado Design Suite
|
Integration with design tool
|
•
Loose coupling with Vivado Design Suite
•
Supports both ISE Design Suite (PlanAhead tool) and Vivado Design Suite
|
•
Tightly integrated into Vivado Design Suite
•
Only supported with Vivado Design Suite
|
Domains addressed
|
Embedded (processor based)
|
All
|
Graphical User Interface
|
Patch Panel-based connectivity for interfaces
|
Schematic/Block-based editing
|
Design Flows
|
Makefile-based
|
Integrated Vivado Design Suite flow
|
Device Family Support
|
•
PlanAhead
™
design tool: Spartan
®
-3, Virtex
®
-4, Virtex-5, Virtex-6,
7 Series devices, Zynq devices
•
Vivado: 7 series devices only (no Zynq device support)
|
•
7 series devices
•
Zynq device
•
UltraScale devices
•
New architectures
|