IOB - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

TRUE

Applied To

FF cells

Constraint Values

TRUE

UCF Example

INST a1_reg[*] IOB = TRUE;

XDC Example

set_property IOB TRUE [get_ports DataOut_pad[*]]

TIP: XDC example 1, above, puts the property on the port itself and causes the flop that drives the IO buffer to be placed inside the pad.

FALSE

Applied To

FF cells

Constraint Values

FALSE

UCF Example

INST b1_reg[*] IOB = FORCE;

XDC Example

set_property IOB TRUE [get_cells a1_reg[*]]

FORCE

Applied To

FF cells

Constraint Values

FORCE

UCF Example

INST q_reg[*] IOB = FALSE;

XDC Example

set_property IOB TRUE [get_cells q_reg[*]]

Note: The Vivado Design Suite does not support this constraint in XDC. Use TRUE instead.

H_SET

Applied To

Cells

Constraint Values

Tool-generated string

UCF Example

N/A

XDC Example

N/A

Note: For more information, see Relative Location (RLOC) in the Constraints Guide (UG625) [Ref 11] . In the Vivado Design Suite, H_SET cells have a property called RPM.

U_SET

Applied To

Cells

Constraint Values

String

UCF Example

INST u0 U_SET = h0; (usually set in UCF)

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

U_SET must be placed in HDL code as an attribute.

For more information, see Relative Location (RLOC) in the Constraints Guide (UG625) [Ref 11] .

RLOC

Applied To

Cells

Constraint Values

XnYn

UCF Example

INST u0 RLOC = X2Y1;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

RLOC must be placed in HDL code as an attribute.

For more information, see Relative Location (RLOC) in the Constraints Guide (UG625) [Ref 11] .

RLOC_ORIGIN

Applied To

Cells

Constraint Values

XnYn

UCF Example

INST u0 RLOC_ORIGIN = X144Y255;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

RLOC_ORIGIN must be placed in HDL code as an attribute.

For more information, see Relative Location (RLOC) in the Constraints Guide (UG625) [Ref 11] .

RPM_GRID

Applied To

Cells

Constraint Values

GRID

UCF Example

INST u0 RPM_GRID = GRID;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

RPM_GRID must be placed in HDL code as an attribute.

For more information, see Relative Location (RLOC) in the Constraints Guide (UG625) [Ref 11] .

USE_RLOC

Applied To

Cells

Constraint Values

TRUE, FALSE

UCF Example

INST u0 USE_RLOC = FALSE;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

RLOC_RANGE

Applied To

Cells

Constraint Values

XnYn:XnYn

UCF Example

INST u0 RLOC_RANGE = X1Y1:X3Y3;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

Create a Pblock with the desired range, and add the RPM cells to the Pblock .

BLKNM

Applied To

Cells

Constraint Values

String

UCF Example

INST u0 BLKNM = blk0;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

HBLKNM

Applied To

Cells, Nets

Constraint Values

String

UCF Example

INST u0 HBLKNM = blk0;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

XBLKNM

Applied To

Cells, Nets

Constraint Values

String

UCF Example

INST u0 XBLKNM = blk0;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

Use BEL PROHIBIT to keep out unrelated logic.

HLUTNM

Applied To

LUT cells

Constraint Values

String

UCF Example

UCF is not allowed, only HDL.

XDC Example

set_property HLUTNM h0 [get_cells {LUT0 LUT1}]

LUTNM

Applied To

LUT cells

Constraint Values

String

UCF Example

UCF is not allowed, only HDL.

XDC Example

set_property LUTNM h0 [get_cells {LUT0 LUT1}]

USE_LUTNM

Applied To

LUT cells

Constraint Values

TRUE, FALSE

UCF Example

INST lut0 USE_LUTNM = FALSE;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.