ILA and VIO Debug IP Cores - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

Use the Vivado logic analyzer to interact with the ILA v2.0 (or later) and/or VIO v2.0 (or later) debug IP cores.

Table: Debug IP Core and Run Time Tool Requirements shows the logic debug IP core compatibility with run time tools.

Table 7-3: Debug IP Core and Run Time Tool Requirements

Debug IP Core and Version

Run Time Tool Requirement

AXI ChipScope Monitor, v3.05a (or earlier)

ChipScope Pro Analyzer

Integrated Controller (ICON), v1.06a (or earlier)

ChipScope Pro Analyzer

Integrated Logic Analyzer (ILA), v1.05a (or earlier)

ChipScope Pro Analyzer

Integrated Logic Analyzer (ILA), v2.0 (or later)

Vivado logic analyzer

Virtual Input/Output (VIO), v1.05a (or earlier)

ChipScope Pro Analyzer

Virtual Input/Output (VIO), v2.0 (or later)

Vivado logic analyzer