From:To Constraints - 2022.2 English - UG911

ISE to Vivado Design Suite Migration Guide (UG911)

Document ID
UG911
Release Date
2022-10-19
Version
2022.2 English

Generally, UCF From:To constraints are converted to either set_max_delay or set_min_delay XDC constraints, with the -from , -to and -through design-dependent arguments.

The intent of UCF constraints is to use the equivalent XDC constraints. While most UCF constraints are net-based, XDC constraints must be constructed to ports and pins.

Helpful XDC commands for these constraints are: all_fanout , get_cells , and get_pins as well as the -from , -to , and -through arguments.

Assigning Timing Group to an Area Group

UCF Example

TIMEGRP clock_grp = AREA_GROUP clock_ag;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

EXCEPT

UCF Example

TIMEGRP my_group = FFS EXCEPT your_group;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

Between Groups

UCF Example

TIMESPEC TS_TIG = FROM reset_ff TO FFS TIG;

XDC Example

Manual conversion is required. Construct a set_false_path that covers the desired paths.

By Net

UCF Example

NET reset TIG;

XDC Example

set_false_path -through [get_nets reset]

A better approach is to find the primary reset port and use:

set_false_path -from [get_ports reset_port]

By Instance

UCF Example

INST reset TIG;

XDC Example

set_false_path -from [get_cells reset]

set_false_path -through [get_cells reset]

set_false_path -to [get_cells reset]

By Pin

UCF Example

PIN ff.d TIG;

XDC Example

set_false_path -to [get_pins ff/D]

set_false_path -from [get_pins ff/C]

set_false_path -through [get_pins lut/I0]

Specific Time Constraints

UCF Example

NET reset TIG = TS_fast TS_even_faster;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

Note: Constraint-specific TIG tries to disable timing through the net, but only for analysis of the two referenced constraints.

MAXSKEW

UCF Example

NET local_clock MAXSKEW = 2ns;

XDC Example

The Vivado Design Suite does not support this constraint in XDC.

MAXDELAY

UCF Example

NET local_clock MAXDELAY = 2ns;

XDC Example

The Vivado Design Suite does not support this constraint in XDC. You can, however, use set_max_delay for specifying the timing requirement for a valid timing path (synchronous start point to synchronous Endpoint).